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library verilog; use verilog.vl_types.all; entity back is port( clk_5m : in vl_logic; rst : in vl_logic; nd_a : in vl_logic;

version 3 d:\lijunyang_software\code_chinaeda\pingpang\pingpang.v pingpang VERILOG VERILOG test.xwv Clocked - - 100000000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEGIN clk_5m 1

ncverilog: 05.30-s007: (c) Copyright 1995-2004 Cadence Design Systems, Inc. TOOL: ncverilog 05.30-s007: Started on Feb 21, 2009 at 15:07:37 ncverilog spi_core_tb.v +h+RTL -f rtl.src +access+rwc

# # Usage: generate.exe vio -f= # -compname=vio -outputdirectory=C:\ISE_designs\CDRE1T1\Verilog_version\code\cspro -devicefamily=Virtex5 -srl16type=2 -asyncinwidth=2 -asyncoutwi

# # Usage: generate.exe icon -f= # -compname=icon -numports=1 -devicefamily=Virtex5 -bscanchain=1 -outputdirectory=C:\ISE_designs\CDRE1T1\Verilog_version\code\cspro

// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2009 by Wilson Snyder. `define hsub v_hier

// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2009 by Wilson Snyder. module v_hier_top2

library verilog; use verilog.vl_types.all; entity cpu is port( clk : in vl_logic; reset : in vl_logic; halt : out vl_logic;

set tool_name "ModelSim (Verilog)" set corner_file_list { {{"Slow Model"} {twice.vo twice_v.sdo}} }

library verilog; use verilog.vl_types.all; entity crc32_d32 is port( data_in : in vl_logic_vector(31 downto 0); clk : in vl_logic; reset