test.tbw

关于乒乓操作的

version 3
d:\lijunyang_software\code_chinaeda\pingpang\pingpang.v
pingpang
VERILOG
VERILOG
test.xwv
Clocked
-
-
100000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk_5m
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
indata
clk_5m
nd
clk_5m
out
clk_5m
rdy
clk_5m
rst
clk_5m
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
out_DIFF
rdy_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk_5m
nd
rst
indata
rdy
out
SIGNAL_ORDER_END
-X-X-X-