ncverilog.log

spi slave 8bit address 1bit r/w 7bit number data

ncverilog: 05.30-s007: (c) Copyright 1995-2004 Cadence Design Systems, Inc.
TOOL:	ncverilog	05.30-s007: Started on Feb 21, 2009 at 15:07:37
ncverilog
	spi_core_tb.v
	+h+RTL
	-f rtl.src
		+access+rwc
		+notimingcheck
		+no_tchk_msg
		+no_specify
		+librescan
		+libext+.v+.vp+.mdlp+.vc+.vh+.vm+.sv
		+define+functional
		+loadpli1=debpli:deb_PLIPtr
		+ncnontcglitch
		+bus_conflict_off
		+incdir+.+../rtl
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/packages/gtech/src_ver
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw01/src_ver
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw02/src_ver
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw06/src_ver
		-y
		../rtl
		-y
		../mem
		./spi_core_tb.v
		-y
		/home_wing/tools/synopsys/2003.12-SP1/SYN/packages/gtech/src_ver
		-y
		/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw01/src_ver
		-y
		/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw02/src_ver
		-y
		/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw06/src_ver
		-v
		../../../../library/xilinx_8.1/verilog/glbl.v
		-y
		../../../../library/xilinx_8.1/verilog/XilinxCoreLib
		-y
		../../../../library/xilinx_8.1/verilog/simprims
		-y
		../../../../library/xilinx_8.1/verilog/unisims
		-v
		../../../../TG901/LIB/IC/sc-x/verilog/csm18ic.v
		-v
		../../../../TG901/LIB/IC/IO/io-il/verilog/iogp_il_csm18ic_verilog.v
ncvlog: *W,NOTIND: unable to access -INCDIR ../rtl (No such file or directory).
file: spi_core_tb.v
ncvlog: *W,LIBNOF: Library file or directory "../rtl" does not exist.
ncvlog: *W,LIBNOF: Library file or directory "../mem" does not exist.
file: ./spi_core_tb.v
module spi_core_tb;
                 |
ncvlog: *W,RECOME (./spi_core_tb.v,3|17): recompiling module/udp worklib.spi_core_tb:v.
	First compiled from line 3 of spi_core_tb.v.
ncvlog: *W,LIBNOF: Library file or directory "../../../../library/xilinx_8.1/verilog/glbl.v" does not exist.
ncvlog: *W,LIBNOF: Library file or directory "../../../../library/xilinx_8.1/verilog/XilinxCoreLib" does not exist.
ncvlog: *W,LIBNOF: Library file or directory "../../../../library/xilinx_8.1/verilog/simprims" does not exist.
ncvlog: *W,LIBNOF: Library file or directory "../../../../library/xilinx_8.1/verilog/unisims" does not exist.
ncvlog: *W,LIBNOF: Library file or directory "../../../../TG901/LIB/IC/sc-x/verilog/csm18ic.v" does not exist.
ncvlog: *W,LIBNOF: Library file or directory "../../../../TG901/LIB/IC/IO/io-il/verilog/iogp_il_csm18ic_verilog.v" does not exist.
ncvlog: *W,LIBNOU: Library "/home_wing/tools/synopsys/2003.12-SP1/SYN/packages/gtech/src_ver" given but not used.
ncvlog: *W,LIBNOU: Library "/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw01/src_ver" given but not used.
ncvlog: *W,LIBNOU: Library "/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw02/src_ver" given but not used.
ncvlog: *W,LIBNOU: Library "/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw06/src_ver" given but not used.
ncvlog: *W,UNBINS: Unbound instance found: uut::spi_core_slave in unit worklib.spi_core_tb:v.
ncvlog: *W,UNBINS: Unbound instance found: uut::spi_core_slave in unit worklib.spi_core_tb:v.
ncvlog: *E,UNBERR: (2) unbound instance(s).
	Total errors/warnings found outside modules and primitives:
		errors: 1, warnings: 15
ncverilog: *E,VLGERR: Error during parsing (status 1), exiting.
TOOL:	ncverilog	05.30-s007: Exiting on Feb 21, 2009 at 15:07:38  (total: 00:00:01)