_primary.vhd

来自「能算出CRC32 Data width 32 bit 的HDL」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity crc32_d32 is
    port(
        data_in         : in     vl_logic_vector(31 downto 0);
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        init            : in     vl_logic;
        crc_out         : out    vl_logic_vector(31 downto 0);
        neg_crc         : out    vl_logic_vector(31 downto 0);
        crc             : out    vl_logic_vector(31 downto 0)
    );
end crc32_d32;