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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
mo : out vl_logic_vector(16 downto 0);
a : in vl_logic_vector(16 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity EXE is
port(
E_RegDes : in vl_logic;
E_ALUSrcB : in vl_logic;
E_ALUcontrol : in vl_logic_vecto
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity \IF\ is
port(
pc : out vl_logic_vector(31 downto 0);
instr : out vl_logic_vector(31 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity datamem is
port(
address : in vl_logic_vector(3 downto 0);
clock : in vl_logic;
data
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffre is
generic(
n : integer := 32
);
port(
clk : in vl_logic;
d : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdivision is
port(
reset : in vl_logic;
F10M : in vl_logic;
Fcycle : out vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity blocking is
port(
clk : in vl_logic;
a : in vl_logic_vector(3 downto 0);
b
gnumakefile
# ******************************************************************************
# ******************************************************************************
# This makefile contains the rules for
gnumakefile
# ******************************************************************************
# ******************************************************************************
# This makefile contains the rules for