_primary.vhd

用VHDL设计具有简单MIPS功能的源码

library verilog;
use verilog.vl_types.all;
entity dffre is
    generic(
        n               : integer := 32
    );
    port(
        clk             : in     vl_logic;
        d               : in     vl_logic_vector;
        q               : out    vl_logic_vector;
        en              : in     vl_logic
    );
end dffre;