_primary.vhd

用VHDL设计具有简单MIPS功能的源码

library verilog;
use verilog.vl_types.all;
entity \IF\ is
    port(
        pc              : out    vl_logic_vector(31 downto 0);
        instr           : out    vl_logic_vector(31 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        Branch          : in     vl_logic;
        WritePC         : in     vl_logic;
        BranchAddr      : in     vl_logic_vector(31 downto 0)
    );
end \IF\;