_primary.vhd

来自「用VHDL设计具有简单MIPS功能的源码」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity datamem is
    port(
        address         : in     vl_logic_vector(3 downto 0);
        clock           : in     vl_logic;
        data            : in     vl_logic_vector(31 downto 0);
        wren            : in     vl_logic;
        q               : out    vl_logic_vector(31 downto 0)
    );
end datamem;