_primary.vhd

用VHDL设计具有简单MIPS功能的源码

library verilog;
use verilog.vl_types.all;
entity EXE is
    port(
        E_RegDes        : in     vl_logic;
        E_ALUSrcB       : in     vl_logic;
        E_ALUcontrol    : in     vl_logic_vector(3 downto 0);
        E_A             : in     vl_logic_vector(31 downto 0);
        E_B             : in     vl_logic_vector(31 downto 0);
        E_I             : in     vl_logic_vector(31 downto 0);
        E_RT            : in     vl_logic_vector(4 downto 0);
        E_RD            : in     vl_logic_vector(4 downto 0);
        ALUResult       : out    vl_logic_vector(31 downto 0);
        mrd             : out    vl_logic_vector(4 downto 0);
        mb              : out    vl_logic_vector(31 downto 0)
    );
end EXE;