_primary.vhd

用verilog编写适中分频器 并且还有测试程序

library verilog;
use verilog.vl_types.all;
entity fdivision is
    port(
        reset           : in     vl_logic;
        F10M            : in     vl_logic;
        Fcycle          : out    vl_logic
    );
end fdivision;