代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
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www.eeworm.com/read/347114/11699564
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/156808/11762807
qmsg xiaolizi1588.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/156456/11802485
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity divf_divf_test_v_tf is
end divf_divf_test_v_tf;
www.eeworm.com/read/345513/11810676
vif match_rec.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file matc
www.eeworm.com/read/155194/11889884
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decQPSK is
port(
clk : in vl_logic;
reset : in vl_logic;
bita : in vl_logic;
www.eeworm.com/read/155192/11890014
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity frame is
generic(
CAP : integer := 0;
SUS : integer := 1
);
port(
clk : in
www.eeworm.com/read/153541/12028847
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity comp1 is
port(
o : out vl_logic;
s : out vl_logic;
a : in vl_logic;
www.eeworm.com/read/152702/12091772
htm st_mult1_srr.htm
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Sat Mar 18 10:37:09 2006
Synplicity Verilog Compiler, versi
www.eeworm.com/read/152702/12091818
srr st_mult1.srr
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Sat Mar 18 10:37:09 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synp
www.eeworm.com/read/152702/12092042
htm st_mult1_srr.htm
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Fri Mar 17 22:06:30 2006
Synplicity Verilog Compiler, ver