match_rec.vif

来自「使用VERILOG实现QPSK信号的匹配滤波」· VIF 代码 · 共 56 行

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  match_rec.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Xilinx

# RTL and technology files
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original -verilog ./match_rec.v
vif_set_top_module -original -top match_rec
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog match_rec.vm
vif_set_top_module -translated -top match_rec 
# Read FSM encoding

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies

# Technology sequential redundancies
vif_set_equiv -translated cnt_Z[1] cnt_fast_Z[1]
vif_set_equiv -translated cnt_Z[0] cnt_fast_Z[0]

# Inversion map points

# Port mappping and directions

# Black box mapping


# Other sequential cells, including multidimensional arrays

# Constant Registers

# Retimed Registers