_primary.vhd

来自「QPSK的VERLOG源码」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity decQPSK is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        bita            : in     vl_logic;
        bitb            : in     vl_logic;
        bit_out         : out    vl_logic
    );
end decQPSK;