test_decqpsk.v

来自「QPSK的VERLOG源码」· Verilog 代码 · 共 33 行

/****************************************************/
//MODULE :test_decQPSK
/***************************************************/
`timescale 1ns/1ns

module test_decQPSK;
reg clk;
reg reset;
reg bita;
reg bitb;
wire bit_out;

always #10 clk=~clk;

initial
begin
reset=1;clk=0;bita=0;bitb=0;
#20 reset=0;bita=1;
#60 bita=0;
#20 bitb=1;
#40 bita=1;bitb=0;
#60 bitb=1;
#20 bita=0;
#40 bita=1;bitb=0;
#80 bitb=1;
#40 bita=0;
#10 $stop;

end

 
 decQPSK DECqpsk(clk,reset,bita,bitb,bit_out);
 endmodule