qpsk.v

来自「QPSK的VERLOG源码」· Verilog 代码 · 共 47 行

/***********************************************/
//MUDULE :QPSK
//encode
/***********************************************/
module QPSKenckde(clk,reset,bit_in,bit_out1,bit_out2);
input bit_in;
input clk;
input reset;
output bit_out1;
output bit_out2;

wire bit_in;
reg bit_out1;
reg bit_out2;

reg ina;
reg inb;
reg flag;

always@(posedge clk)
begin
if(reset)
  begin ina=0;inb=0;flag=0;bit_out1=0; bit_out2=0; end
else

  begin
  
  if(flag)
     begin ina=bit_in; flag=flag+1;end
  else
     begin inb=bit_in;flag=flag+1;end   
  end//????
  
  //??
  if(bit_out1^bit_out2)
    begin
      bit_out1=inb^bit_out1;
      bit_out2=ina^bit_out2;
    end
  else
     begin
      bit_out1=ina^bit_out1;
      bit_out2=inb^bit_out2;
     end
  
end
endmodule