xiaolizi1588.map.qmsg

ic读卡器 能读ic电话卡并按时记费

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 13 21:26:41 2006 " "Info: Processing started: Thu Apr 13 21:26:41 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off xiaolizi1588 -c xiaolizi1588 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off xiaolizi1588 -c xiaolizi1588 --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../xiaolizi1588.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../xiaolizi1588.v" { { "Info" "ISGN_ENTITY_NAME" "1 xiaolizi1588 " "Info: Found entity 1: xiaolizi1588" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "xiaolizi1588 " "Info: Elaborating entity \"xiaolizi1588\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 xiaolizi1588.v(23) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(23): truncated value with size 32 to match size of target (11)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(27) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(27): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(32) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(32): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(38) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(38): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(45) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(45): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(52) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(52): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(53) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(53): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 53 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(54) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(54): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(59) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(59): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(61) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(61): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(62) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(62): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 xiaolizi1588.v(63) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(63): truncated value with size 32 to match size of target (3)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(66) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(66): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(67) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(67): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(70) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(70): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 70 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(72) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(72): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(73) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(73): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 73 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(75) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(75): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 75 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(78) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(78): truncated value with size 32 to match size of target (4)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(79) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(79): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 79 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(80) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(80): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 80 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(85) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(85): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(86) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(86): truncated value with size 32 to match size of target (1)" {  } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 86 0 0 } }  } 0}