st_mult1.srr

veilog实现的状态机乘法器.可以参考

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Sat Mar 18 10:37:09 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"D:\Program_Files\synplify81\fpga_81\lib\altera\altera.v"
@I::"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v"
Verilog syntax check successful!
File G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v changed - recompiling
Selecting top level module st_mult1
@N:"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":1:7:1:14|Synthesizing module st_mult1

@W: CG296 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":24:8:24:20|Incomplete sensitivity list - assuming completeness
@W: CG290 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":35:32:35:40|Referenced variable cheng_shu is not in sensitivity list
@W: CG290 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":33:32:33:44|Referenced variable bei_cheng_shu is not in sensitivity list
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal result[31:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal bei_cheng_shu_Temp[31:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal count[4:0], probably caused by a missing assignment in an if or case stmt
@W: CL113 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Feedback mux created for signal ok.
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal ok, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal cheng_shu_temp[15:0], probably caused by a missing assignment in an if or case stmt
@N: CL201 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":17:1:17:6|Trying to extract state machine for register current_state
Extracted state machine for register current_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Mar 18 10:37:11 2006

###########################################################[
Version 8.1
Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved


Warning: Found 37 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[0]
1) instance work.st_mult1(verilog)-result[31:0], output net "result[0]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[1]
2) instance work.st_mult1(verilog)-result[31:0], output net "result[1]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[2]
3) instance work.st_mult1(verilog)-result[31:0], output net "result[2]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[3]
4) instance work.st_mult1(verilog)-result[31:0], output net "result[3]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[4]
5) instance work.st_mult1(verilog)-result[31:0], output net "result[4]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[5]
6) instance work.st_mult1(verilog)-result[31:0], output net "result[5]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)