st_mult1.tlg

来自「veilog实现的状态机乘法器.可以参考」· TLG 代码 · 共 20 行

Selecting top level module st_mult1
@N:"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":1:7:1:14|Synthesizing module st_mult1

@W: CG296 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":24:8:24:20|Incomplete sensitivity list - assuming completeness
@W: CG290 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":35:32:35:40|Referenced variable cheng_shu is not in sensitivity list
@W: CG290 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":33:32:33:44|Referenced variable bei_cheng_shu is not in sensitivity list
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal result[31:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal bei_cheng_shu_Temp[31:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal count[4:0], probably caused by a missing assignment in an if or case stmt
@W: CL113 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Feedback mux created for signal ok.
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal ok, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Latch generated from always block for signal cheng_shu_temp[15:0], probably caused by a missing assignment in an if or case stmt
@N: CL201 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":17:1:17:6|Trying to extract state machine for register current_state
Extracted state machine for register current_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11