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VHDL 的代码
usb_new_sieinterface_rtl.vhdl
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---- File >>> usb_new_sieinterface_rtl.vhdl
---- Iden >>> 960312-17:09:39
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---- Project: USB Developm
usb_new_sieinterface_ent.vhdl
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---- File >>> usb_new_siehandler_ent.vhdl
---- Iden >>> 960312-17:09:34
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---- Project: USB Developmen
usb_new_clkrec_rtl.vhdl
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---- File >>> usb_new_clkrec_rtl.vhdl
---- Iden >>> 951017-16:10:26
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---- Project: USB Development
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usb_new_pck_configuration.vhdl
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---- File >>> usb_new_pck_configuration.vhdl
---- Iden >>> 981130-10:32:49
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---- Project:
usb_new_upstreamled_rtl.vhdl
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---- File >>> usb_new_upstreamled_rtl.vhdl
---- Iden >>> 980306-10:26:05
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---- Project: USB De
usb_new_timers_sf_ent.vhdl
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---- File >>> usb_new_timers_sf_ent.vhdl
---- Iden >>> 970604-14:16:07
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---- Project: USB Development
usb_new_timers_sf_rtl.vhdl
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---- File >>> usb_new_timers_sf_rtl.vhdl
---- Iden >>> 970604-14:16:12
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---- Project: USB Development
usb_new_sie_ent.vhdl
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---- File >>> usb_new_sie_ent.vhdl
---- Iden >>> 960123-09:12:02
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---- Project: USB Development
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0sn7485.mgf
V 000037 11 116 1047634283301 e_and2
E e_and2 VHDL
L IEEE;
U ieee.std_logic_1164;
P in1 _in std_logic
P in2 _in std_logic
P out1 _out std_logic
X e_and2
V 000037 11 136 1047634283321 e_and3
E e_and3 V
adc0809 vhdl控制程序.txt
--文件名：ADC0809.vhd
--功能：基于VHDL语言，实现对ADC0809简单控制
--说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系
--统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。
--最后修改日期：2004.3.20
library ieee;
use ieee.std_lo