vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Tue Nov 04 09:38:37 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ic_and is
    port (    
	IN1:       IN     STD_LOGIC;    
	IN2:       IN     STD_LOGIC;    
	\out\:     OUT    STD_LOGIC);
end ic_and;