vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Wed Oct 22 08:54:20 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity rec2p is
    port (    
	AC1:       INOUT  STD_LOGIC;    
	AC2:       INOUT  STD_LOGIC;    
	M:         INOUT  STD_LOGIC;    
	P:         INOUT  STD_LOGIC);
end rec2p;