vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Fri Dec 19 00:01:13 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity fci_10061913_102clf is
    port (    
	A1:        INOUT  STD_LOGIC;    
	A10:       INOUT  STD_LOGIC;    
	A11:       INOUT  STD_LOGIC;    
	A12:       INOUT  STD_LOGIC;    
	A13:       INOUT  STD_LOGIC;    
	A14:       INOUT  STD_LOGIC;    
	A15:       INOUT  STD_LOGIC;    
	A16:       INOUT  STD_LOGIC;    
	A17:       INOUT  STD_LOGIC;    
	A18:       INOUT  STD_LOGIC;    
	A19:       INOUT  STD_LOGIC;    
	A2:        INOUT  STD_LOGIC;    
	A20:       INOUT  STD_LOGIC;    
	A21:       INOUT  STD_LOGIC;    
	A22:       INOUT  STD_LOGIC;    
	A23:       INOUT  STD_LOGIC;    
	A24:       INOUT  STD_LOGIC;    
	A25:       INOUT  STD_LOGIC;    
	A26:       INOUT  STD_LOGIC;    
	A27:       INOUT  STD_LOGIC;    
	A28:       INOUT  STD_LOGIC;    
	A29:       INOUT  STD_LOGIC;    
	A3:        INOUT  STD_LOGIC;    
	A30:       INOUT  STD_LOGIC;    
	A31:       INOUT  STD_LOGIC;    
	A32:       INOUT  STD_LOGIC;    
	A33:       INOUT  STD_LOGIC;    
	A34:       INOUT  STD_LOGIC;    
	A35:       INOUT  STD_LOGIC;    
	A36:       INOUT  STD_LOGIC;    
	A37:       INOUT  STD_LOGIC;    
	A38:       INOUT  STD_LOGIC;    
	A39:       INOUT  STD_LOGIC;    
	A4:        INOUT  STD_LOGIC;    
	A40:       INOUT  STD_LOGIC;    
	A41:       INOUT  STD_LOGIC;    
	A42:       INOUT  STD_LOGIC;    
	A43:       INOUT  STD_LOGIC;    
	A44:       INOUT  STD_LOGIC;    
	A45:       INOUT  STD_LOGIC;    
	A46:       INOUT  STD_LOGIC;    
	A47:       INOUT  STD_LOGIC;    
	A48:       INOUT  STD_LOGIC;    
	A49:       INOUT  STD_LOGIC;    
	A5:        INOUT  STD_LOGIC;    
	A6:        INOUT  STD_LOGIC;    
	A7:        INOUT  STD_LOGIC;    
	A8:        INOUT  STD_LOGIC;    
	A9:        INOUT  STD_LOGIC;    
	B1:        INOUT  STD_LOGIC;    
	B10:       INOUT  STD_LOGIC;    
	B11:       INOUT  STD_LOGIC;    
	B12:       INOUT  STD_LOGIC;    
	B13:       INOUT  STD_LOGIC;    
	B14:       INOUT  STD_LOGIC;    
	B15:       INOUT  STD_LOGIC;    
	B16:       INOUT  STD_LOGIC;    
	B17:       INOUT  STD_LOGIC;    
	B18:       INOUT  STD_LOGIC;    
	B19:       INOUT  STD_LOGIC;    
	B2:        INOUT  STD_LOGIC;    
	B20:       INOUT  STD_LOGIC;    
	B21:       INOUT  STD_LOGIC;    
	B22:       INOUT  STD_LOGIC;    
	B23:       INOUT  STD_LOGIC;    
	B24:       INOUT  STD_LOGIC;    
	B25:       INOUT  STD_LOGIC;    
	B26:       INOUT  STD_LOGIC;    
	B27:       INOUT  STD_LOGIC;    
	B28:       INOUT  STD_LOGIC;    
	B29:       INOUT  STD_LOGIC;    
	B3:        INOUT  STD_LOGIC;    
	B30:       INOUT  STD_LOGIC;    
	B31:       INOUT  STD_LOGIC;    
	B32:       INOUT  STD_LOGIC;    
	B33:       INOUT  STD_LOGIC;    
	B34:       INOUT  STD_LOGIC;    
	B35:       INOUT  STD_LOGIC;    
	B36:       INOUT  STD_LOGIC;    
	B37:       INOUT  STD_LOGIC;    
	B38:       INOUT  STD_LOGIC;    
	B39:       INOUT  STD_LOGIC;    
	B4:        INOUT  STD_LOGIC;    
	B40:       INOUT  STD_LOGIC;    
	B41:       INOUT  STD_LOGIC;    
	B42:       INOUT  STD_LOGIC;    
	B43:       INOUT  STD_LOGIC;    
	B44:       INOUT  STD_LOGIC;    
	B45:       INOUT  STD_LOGIC;    
	B46:       INOUT  STD_LOGIC;    
	B47:       INOUT  STD_LOGIC;    
	B48:       INOUT  STD_LOGIC;    
	B49:       INOUT  STD_LOGIC;    
	B5:        INOUT  STD_LOGIC;    
	B6:        INOUT  STD_LOGIC;    
	B7:        INOUT  STD_LOGIC;    
	B8:        INOUT  STD_LOGIC;    
	B9:        INOUT  STD_LOGIC);
end fci_10061913_102clf;