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VHDL 的代码
msi.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
vhdl.txt
用VHDL语言编写一个乘法器程序
基于BOOTH算法的
-- Company:
-- Engineer:savage
--
-- Create Date: 19:31:17 03/05/06
-- Design Name:
-- Module Name: mp - Behavioral
-- Project Name:
-- Target Device:
-
mulpar.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.module_line_one.all;
--use work.module_column_eight.all;
--use work.module_li
code.vhdl
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;
entity code is
port(
RST: in std_logic;
memory.vhdl
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;
entity memory is
port(
T3: in std_logic