vhdl.txt

用VHDL语言编写的一个乘法器校程序 是基于BOOTH算法的

用VHDL语言编写一个乘法器程序 
基于BOOTH算法的 
-- Company: 
-- Engineer:savage 
-- 
-- Create Date: 19:31:17 03/05/06 
-- Design Name: 
-- Module Name: mp - Behavioral 
-- Project Name: 
-- Target Device: 
-- Tool versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision: 
-- Revision 0.01 - File Created 
-- Additional Comments: 
-- 
-------------------------------------------------------------------------------- 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

---- Uncomment the following library declaration if instantiating 
---- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity mp is 
Port ( ai,bi : in std_logic_vector(31 downto 0); 
done : out std_logic; 
op : out std_logic_vector(63 downto 0)); 
end mp; 
architecture Behavioral of mp is 
begin 

process(ai,bi) 
variable a,b,m : std_logic_vector( 31 downto 0); 
variable cp: std_logic_vector( 1 downto 0); 
variable t: std_logic ; 
variable counter: integer; 
begin 
counter:=0; 
t:='0'; 
a:=ai; 
b:=bi; 
m:="00000000000000000000000000000000"; 
cp:=b(0)&'0'; 
done<='0'; 
while counter<32 loop 
case cp is 
when "10"=> m:=m-a; 
when "01"=> m:=m+a; 
when others=>m:=m; 
end case; 
t:=b(0); 
b:=m(0)&b(31 downto 1); 
m:=m(31)&m(31 downto 1); 
cp:=b(0)&t; 
counter:=counter+1; 
end loop; 
op<= m&b; 
done<='1'; 
end process; 
end Behavioral; 

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