📄 mulpar.vhdl
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.module_line_one.all;
--use work.module_column_eight.all;
--use work.module_line_mid.all;
--use work.module_line_last.all;
use work.my_component.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity MulPar is
port(A:in std_logic_vector(7 downto 0); --input 8 bits multiplier
B:in std_logic_vector(7 downto 0); --input 8 bits multiplicand
P:out std_logic_vector(15 downto 0);--output 16 bits result
CLK:in std_logic); --input clock signal
end MulPar;
architecture Behavioral of MulPar is
--step two :componet define
signal a_in:std_logic_vector(7 downto 0); --A input get through D trigger
signal b_in:std_logic_vector(7 downto 0); --B input get through D trigger
signal p_in:std_logic_vector(15 downto 0); --P output get through D trigger
signal c0:std_logic_vector(6 downto 0); --carry of line 0
signal o0:std_logic_vector(7 downto 1); --result of line 0
signal c1:std_logic_vector(6 downto 0); --carry of line 1
signal o1:std_logic_vector(7 downto 1); --result of line 1
signal c2:std_logic_vector(6 downto 0); --carry of line 2
signal o2:std_logic_vector(7 downto 1); --result of line 2
signal c3:std_logic_vector(6 downto 0); --carry of line 3
signal o3:std_logic_vector(7 downto 1); --result of line 3
signal c4:std_logic_vector(6 downto 0); --carry of line 4
signal o4:std_logic_vector(7 downto 1); --result of line 4
signal c5:std_logic_vector(6 downto 0); --carry of line 5
signal o5:std_logic_vector(7 downto 1); --result of line 5
signal c6:std_logic_vector(6 downto 0); --carry of line 6
signal o6:std_logic_vector(7 downto 1); --result of line 6
signal c7:std_logic_vector(6 downto 0); --carry of line 7
signal o7:std_logic_vector(7 downto 1); --result of line 7
signal c8:std_logic_vector(6 downto 0); --carry of line 8
--------------------------------------------------------------------------------
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begin
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--step one :tigger event input and output
--input A
D_EVENT_1: process(CLK) is
begin
if( CLK'event and CLK = '1') then --up edge event and then input A
a_in <= A;
end if;
end process D_EVENT_1;
--input B
D_EVENT_2: process(CLK) is
begin
if( CLK'event and CLK = '1') then --up edge event and then input B
b_in <= B;--input
end if;
end process D_EVENT_2;
--output P
D_EVENT_3: process(CLK) is
begin
if( CLK'event and CLK = '1') then --up edge event and then output P
P <=p_in;
end if;
end process D_EVENT_3;
------------------------------------------------------------------------------------------
--step three: operate and get result
--OPERATE_ROW_ZERO
OPERATE_ROW_ZERO: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(0)) is
begin
U00:COMPONENT module_line_one PORT MAP(a_in(0),b_in(0),c0(0),p_in(0)); --MODULE ROW 0 COLUMN 0
u01:COMPONENT module_line_one port map(a_in(0),b_in(1),c0(1),o0(1)); --MODULE ROW 0 COLUMN 1
u02:COMPONENT module_line_one port map(a_in(0),b_in(2),c0(2),o0(2)); --MODULE ROW 0 COLUMN 2
u03:COMPONENT module_line_one port map(a_in(0),b_in(3),c0(3),o0(3)); --MODULE ROW 0 COLUMN 3
u04:COMPONENT module_line_one port map(a_in(0),b_in(4),c0(4),o0(4)); --MODULE ROW 0 COLUMN 4
u05:COMPONENT module_line_one port map(a_in(0),b_in(5),c0(5),o0(5)); --MODULE ROW 0 COLUMN 5
u06:COMPONENT module_line_one port map(a_in(0),b_in(6),c0(6),o0(6)); --MODULE ROW 0 COLUMN 6
u07:COMPONENT MODULE_COLUMN_EIGHT port map(a_in(0),b_in(7),o0(7)); --MODULE ROW 0 COLUMN 7
end process OPERATE_ROW_ZERO;
--OPERATE_ROW_ONE
OPERATE_ROW_ONE: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(1),
c0(0),c0(1),c0(2),c0(3),c0(4),c0(5),c0(6),
o0(1),o0(2),o0(3),o0(4),o0(5),o0(6),o0(7)) is
begin
MODULE_LINE_MID(a_in(1),b_in(0),c0(0),o0(1),c1(0),p_in(1)); --MODULE ROW 1 COLUMN 0
MODULE_LINE_MID(a_in(1),b_in(1),c0(1),o0(2),c1(1),o1(1)); --MODULE ROW 1 COLUMN 1
MODULE_LINE_MID(a_in(1),b_in(2),c0(2),o0(3),c1(2),o1(2)); --MODULE ROW 1 COLUMN 2
MODULE_LINE_MID(a_in(1),b_in(3),c0(3),o0(4),c1(3),o1(3)); --MODULE ROW 1 COLUMN 3
MODULE_LINE_MID(a_in(1),b_in(4),c0(4),o0(5),c1(4),o1(4)); --MODULE ROW 1 COLUMN 4
MODULE_LINE_MID(a_in(1),b_in(5),c0(5),o0(6),c1(5),o1(5)); --MODULE ROW 1 COLUMN 5
MODULE_LINE_MID(a_in(1),b_in(6),c0(6),o0(7),c1(6),o1(6)); --MODULE ROW 1 COLUMN 6
MODULE_COLUMN_EIGHT(a_in(1),b_in(7),o1(7)); --MODULE ROW 1 COLUMN 7
end process OPERATE_ROW_ONE;
--OPERATE_ROW_TWO
OPERATE_ROW_TWO: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(2),
c1(0),c1(1),c1(2),c1(3),c1(4),c1(5),c1(6),
o1(1),o1(2),o1(3),o1(4),o1(5),o1(6),o1(7)) is
begin
MODULE_LINE_MID(a_in(2),b_in(0),c1(0),o1(1),c2(0),p_in(2)); --MODULE ROW 2 COLUMN 0
MODULE_LINE_MID(a_in(2),b_in(1),c1(1),o1(2),c2(1),o2(1)); --MODULE ROW 2 COLUMN 1
MODULE_LINE_MID(a_in(2),b_in(2),c1(2),o1(3),c2(2),o2(2)); --MODULE ROW 2 COLUMN 2
MODULE_LINE_MID(a_in(2),b_in(3),c1(3),o1(4),c2(3),o2(3)); --MODULE ROW 2 COLUMN 3
MODULE_LINE_MID(a_in(2),b_in(4),c1(4),o1(5),c2(4),o2(4)); --MODULE ROW 2 COLUMN 4
MODULE_LINE_MID(a_in(2),b_in(5),c1(5),o1(6),c2(5),o2(5)); --MODULE ROW 2 COLUMN 5
MODULE_LINE_MID(a_in(2),b_in(6),c1(6),o1(7),c2(6),o2(6)); --MODULE ROW 2 COLUMN 6
MODULE_COLUMN_EIGHT(a_in(2),b_in(7),o2(7)); --MODULE ROW 2 COLUMN 7
end process OPERATE_ROW_TWO;
--OPERATE_ROW_THREE
OPERATE_ROW_THREE: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(3),
c2(0),c2(1),c2(2),c2(3),c2(4),c2(5),c2(6),
o2(1),o2(2),o2(3),o2(4),o2(5),o2(6),o2(7)) is
begin
MODULE_LINE_MID(a_in(3),b_in(0),c2(0),o2(1),c3(0),p_in(3)); --MODULE ROW 3 COLUMN 0
MODULE_LINE_MID(a_in(3),b_in(1),c2(1),o2(2),c3(1),o3(1)); --MODULE ROW 3 COLUMN 1
MODULE_LINE_MID(a_in(3),b_in(2),c2(2),o2(3),c3(2),o3(2)); --MODULE ROW 3 COLUMN 2
MODULE_LINE_MID(a_in(3),b_in(3),c2(3),o2(4),c3(3),o3(3)); --MODULE ROW 3 COLUMN 3
MODULE_LINE_MID(a_in(3),b_in(4),c2(4),o2(5),c3(4),o3(4)); --MODULE ROW 3 COLUMN 4
MODULE_LINE_MID(a_in(3),b_in(5),c2(5),o2(6),c3(5),o3(5)); --MODULE ROW 3 COLUMN 5
MODULE_LINE_MID(a_in(3),b_in(6),c2(6),o2(7),c3(6),o3(6)); --MODULE ROW 3 COLUMN 6
MODULE_COLUMN_EIGHT(a_in(3),b_in(7),o3(7)); --MODULE ROW 3 COLUMN 7
end process OPERATE_ROW_THREE;
--OPERATE_ROW_FOUR
OPERATE_ROW_FOUR: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(4),
c3(0),c3(1),c3(2),c3(3),c3(4),c3(5),c3(6),
o3(1),o3(2),o3(3),o3(4),o3(5),o3(6),o3(7)) is
begin
MODULE_LINE_MID(a_in(4),b_in(0),c3(0),o3(1),c4(0),p_in(4)); --MODULE ROW 4 COLUMN 0
MODULE_LINE_MID(a_in(4),b_in(1),c3(1),o3(2),c4(1),o4(1)); --MODULE ROW 4 COLUMN 1
MODULE_LINE_MID(a_in(4),b_in(2),c3(2),o3(3),c4(2),o4(2)); --MODULE ROW 4 COLUMN 2
MODULE_LINE_MID(a_in(4),b_in(3),c3(3),o3(4),c4(3),o4(3)); --MODULE ROW 4 COLUMN 3
MODULE_LINE_MID(a_in(4),b_in(4),c3(4),o3(5),c4(4),o4(4)); --MODULE ROW 4 COLUMN 4
MODULE_LINE_MID(a_in(4),b_in(5),c3(5),o3(6),c4(5),o4(5)); --MODULE ROW 4 COLUMN 5
MODULE_LINE_MID(a_in(4),b_in(6),c3(6),o3(7),c4(6),o4(6)); --MODULE ROW 4 COLUMN 6
MODULE_COLUMN_EIGHT(a_in(4),b_in(7),o4(7)); --MODULE ROW 4 COLUMN 7
end process OPERATE_ROW_FOUR;
--OPERATE_ROW_FIVE
OPERATE_ROW_FIVE: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(5),
c4(0),c4(1),c4(2),c4(3),c4(4),c4(5),c4(6),
o4(1),o4(2),o4(3),o4(4),o4(5),o4(6),o4(7)) is
begin
MODULE_LINE_MID(a_in(5),b_in(0),c4(0),o4(1),c5(0),p_in(5)); --MODULE ROW 5 COLUMN 0
MODULE_LINE_MID(a_in(5),b_in(1),c4(1),o4(2),c5(1),o5(1)); --MODULE ROW 5 COLUMN 1
MODULE_LINE_MID(a_in(5),b_in(2),c4(2),o4(3),c5(2),o5(2)); --MODULE ROW 5 COLUMN 2
MODULE_LINE_MID(a_in(5),b_in(3),c4(3),o4(4),c5(3),o5(3)); --MODULE ROW 5 COLUMN 3
MODULE_LINE_MID(a_in(5),b_in(4),c4(4),o4(5),c5(4),o5(4)); --MODULE ROW 5 COLUMN 4
MODULE_LINE_MID(a_in(5),b_in(5),c4(5),o4(6),c5(5),o5(5)); --MODULE ROW 5 COLUMN 5
MODULE_LINE_MID(a_in(5),b_in(6),c4(6),o4(7),c5(6),o5(6)); --MODULE ROW 5 COLUMN 6
MODULE_COLUMN_EIGHT(a_in(5),b_in(7),o5(7)); --MODULE ROW 5 COLUMN 7
end process OPERATE_ROW_FIVE;
--OPERATE_ROW_SIX
OPERATE_ROW_SIX: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(6),
c5(0),c5(1),c5(2),c5(3),c5(4),c5(5),c5(6),
o5(1),o5(2),o5(3),o5(4),o5(5),o5(6),o5(7)) is
begin
MODULE_LINE_MID(a_in(6),b_in(0),c5(0),o5(1),c6(0),p_in(6)); --MODULE ROW 6 COLUMN 0
MODULE_LINE_MID(a_in(6),b_in(1),c5(1),o5(2),c6(1),o6(1)); --MODULE ROW 6 COLUMN 1
MODULE_LINE_MID(a_in(6),b_in(2),c5(2),o5(3),c6(2),o6(2)); --MODULE ROW 6 COLUMN 2
MODULE_LINE_MID(a_in(6),b_in(3),c5(3),o5(4),c6(3),o6(3)); --MODULE ROW 6 COLUMN 3
MODULE_LINE_MID(a_in(6),b_in(4),c5(4),o5(5),c6(4),o6(4)); --MODULE ROW 6 COLUMN 4
MODULE_LINE_MID(a_in(6),b_in(5),c5(5),o5(6),c6(5),o6(5)); --MODULE ROW 6 COLUMN 5
MODULE_LINE_MID(a_in(6),b_in(6),c5(6),o5(7),c6(6),o6(6)); --MODULE ROW 6 COLUMN 6
MODULE_COLUMN_EIGHT(a_in(6),b_in(7),o6(7)); --MODULE ROW 6 COLUMN 7
end process OPERATE_ROW_SIX;
--OPERATE_ROW_SEVENT
OPERATE_ROW_SEVENT: process (b_in(0),b_in(1),b_in(2),b_in(3),b_in(4),b_in(5),b_in(6),b_in(7),
a_in(7),
c6(0),c6(1),c6(2),c6(3),c6(4),c6(5),c6(6),
o6(1),o6(2),o6(3),o6(4),o6(5),o6(6),o6(7)) is
begin
MODULE_LINE_MID(a_in(7),b_in(0),c6(0),o6(1),c7(0),p_in(7)); --MODULE ROW 7 COLUMN 0
MODULE_LINE_MID(a_in(7),b_in(1),c6(1),o6(2),c7(1),o7(1)); --MODULE ROW 7 COLUMN 1
MODULE_LINE_MID(a_in(7),b_in(2),c6(2),o6(3),c7(2),o7(2)); --MODULE ROW 7 COLUMN 2
MODULE_LINE_MID(a_in(7),b_in(3),c6(3),o6(4),c7(3),o7(3)); --MODULE ROW 7 COLUMN 3
MODULE_LINE_MID(a_in(7),b_in(4),c6(4),o6(5),c7(4),o7(4)); --MODULE ROW 7 COLUMN 4
MODULE_LINE_MID(a_in(7),b_in(5),c6(5),o6(6),c7(5),o7(5)); --MODULE ROW 7 COLUMN 5
MODULE_LINE_MID(a_in(7),b_in(6),c6(6),o6(7),c7(6),o7(6)); --MODULE ROW 7 COLUMN 6
MODULE_COLUMN_EIGHT(a_in(7),b_in(7),o6(7)); --MODULE ROW 7 COLUMN 7
end process OPERATE_ROW_SEVENT;
--OPERATE_ROW_EIGHT
OPERATE_ROW_EIGHT: process (c7(0),c7(1),c7(2),c7(3),c7(4),c7(5),c7(6),
o7(1),o7(2),o7(3),o7(4),o7(5),o7(6),o7(7)) is
begin
MODULE_LINE_LAST(c7(0),o7(1),0,c8(0),p_in(8)); --MODULE ROW 8 COLUMN 0
MODULE_LINE_LAST(c7(1),o7(2),c8(0),c8(1),p_in(9)); --MODULE ROW 8 COLUMN 1
MODULE_LINE_LAST(c7(2),o7(3),c8(1),c8(2),p_in(10)); --MODULE ROW 8 COLUMN 2
MODULE_LINE_LAST(c7(3),o7(4),c8(2),c8(3),p_in(11)); --MODULE ROW 8 COLUMN 3
MODULE_LINE_LAST(c7(4),o7(5),c8(3),c8(4),p_in(12)); --MODULE ROW 8 COLUMN 4
MODULE_LINE_LAST(c7(5),o7(6),c8(4),c8(5),p_in(13)); --MODULE ROW 8 COLUMN 5
MODULE_LINE_LAST(c7(6),o7(7),c8(5),p_in(15),p_in(14)); --MODULE ROW 8 COLUMN 6
end process OPERATE_ROW_EIGHT;
end Behavioral;
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