memory.vhdl

16位cpu设计VHDL源码

library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;

entity memory is
port(
	T3: in std_logic;
	MRD_C: in std_logic;
	MWR_C: in std_logic;
	Rtemp: out std_logic_vector(7 downto 0);
	data: in std_logic_vector(7 downto 0);
	nMRD: out std_logic;
	nMWR: out std_logic);
end memory;

architecture Behavioral of memory is
begin
	process(T3, MRD_C, MWR_C)
	begin
		nMRD <= '1';
		nMWR <= '1';
		if(T3 = '1' and MWR_C = '1') then --取数
			nMWR <= '0';
			nMRD <= '1';
		elsif(T3 = '1' and MRD_C = '1') then --取数
			nMRD <= '0';
			nMWR <= '1';
		end if;
	end process;
    	Rtemp <= data;
end Behavioral;