msi.vhdl

来自「这是一个用VHDL写的简易的CPU的程序」· VHDL 代码 · 共 46 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity msi is
    Port ( mci : in std_logic_vector(4 downto 0);
           t0 : in std_logic;
           ncs : out std_logic;
           nwr : out std_logic;
           nrd : out std_logic;
           nbl : out std_logic;
           nbh : out std_logic;
			  readm:out std_logic;
			  writem:out std_logic);
end msi;

architecture main of msi is

begin
  	process(t0,mci)
	begin
		if t0='0' then
		ncs<='1';
		nwr<='1';
		nrd<='1';
		nbl<='1';
		nbh<='1';
		elsif t0='1' and t0'event then
		ncs<=not mci(4);
		nwr<=not mci(3);
		nrd<=not mci(2);
		nbl<=not mci(1);
		nbh<=not mci(0);
		end if; 
	end process;
	readm<=mci(4)and mci(2);
	writem<=mci(4)and mci(3);

end main;