code.vhdl

16位cpu设计VHDL源码

library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;

entity code is
port(
	RST: in std_logic;
	T0: in std_logic;
	T1: in std_logic;
	clk: in std_logic;
	PCupdate: in std_logic;
	PCnew: in std_logic_vector(15 downto 0);
	IRnew: in std_logic_vector(15 downto 0);
	PCload: out std_logic;
	IRout: out std_logic_vector(15 downto 0);
	PCout: out std_logic_vector(15 downto 0));
end code;

architecture Behavioral of code is
component bufgp
	port(I: in std_logic; O: out std_logic);
end component;
signal clkgp: std_logic;
signal PC, IR: std_logic_vector(15 downto 0);
begin
	u1: bufgp port map(I => clk, O => clkgp);
	process(T0, T1, RST, PCupdate, clkgp)
	begin
		if(RST = '0') then
			PCload <= '0';
			IR <= (others => '0');
			PC <= (others => '0');
		elsif(PCupdate = '1') then
			PCload <= '0';
			PC <= PCnew;
		elsif(T0 = '1') then
			PCload <= '1';
			PCout <= PC;
			if(IRnew /= "ZZZZZZZZZZZZZZZZ") then
				IR <= IRnew;
			end if;
		elsif(T1 = '1' and T1' event) then
			PCload <= '0';
			IRout <= IR;
			PC <= PC + 1;	
		else
			PCload <= '0';
		end if;
	end process;
end Behavioral;