代码搜索：REF

找到约 10,000 项符合「REF」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/144120/12812670

ref vli.ref

strValue = first string strValue = second string minValue = 1 maxValue = 3.141590e+000 range1 = [1.000000e+000, 3.141590e+000] range2 = [2, 2] range2 = [1, 3] longBinaryValue converted to binary is: 1
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www.eeworm.com/read/144120/12812677

ref leaf.ref

****************************************************************************** * Leaf Search ****************************************************************************** Warning: Design oaVerilogInT
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www.eeworm.com/read/144120/12812682

ref param.ref

****************************************************************************** * No Explode, No EMH ****************************************************************************** Warning: Binary opera
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www.eeworm.com/read/144120/12812695

ref unbound.ref

// Verilog file for cell "top" view "netlist" // Language Version: 2001 module top (); wire VSS; leaf I0 ( .BUS({VSS,VSS,VSS,VSS,VSS,VSS,VSS,VSS}), .SCALAR(VSS));
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www.eeworm.com/read/144120/12812711

ref width.ref

****************************************************************************** * No Explode, No EMH ****************************************************************************** Contents of width_des
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www.eeworm.com/read/144120/12812735

ref datatype.ref

****************************************************************************** * No Explode, No EMH ****************************************************************************** Warning: Always block
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www.eeworm.com/read/144120/12812744

ref filesys.ref

****************************************************************************** * FileSys Leafs ****************************************************************************** Contents of fileSys.INVX1.
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www.eeworm.com/read/144120/12812747

ref ansiports.ref

****************************************************************************** * No Explode, No EMH ****************************************************************************** Warning: Binary opera
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www.eeworm.com/read/144120/12812752

ref globaltop.ref

// Verilog file for cell "top" view "netlist" // Language Version: 2001 module global1 ( l1_in, l1_out); input [31:0] l1_in; output l1_out; wire l1_reg; endmodule // global1
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www.eeworm.com/read/144120/12812759

ref forward.ref

****************************************************************************** * No Explode, No EMH ****************************************************************************** Contents of forward_d
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