leaf.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* Leaf Search
******************************************************************************
Warning: Design oaVerilogInTestLeafLib.noTop.prim does not have a top module
Contents of leaf.top.netlist
    Contents of TOP module top
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'x[0:1]' (ModBusNet)
            Net: 'n1,n2' (ModBundleNet)
            Net: 'n1' (ModScalarNet)
            Net: 'n2' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		scalarLeaf
        	ViewName:		prim
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		scalarLeaf
        	ViewName:		prim
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I3
        	LibName:		oaVerilogInTestAltLeafLib
        	CellName:		noOrder
        	ViewName:		prim
        	Master Cell Name:	noOrder
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I4
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		blackBox1
        	ViewName:		abstract
        	Master Cell Name:	blackBox1
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I5
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		blackBox2
        	ViewName:		abstract
        	Master Cell Name:	blackBox2
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I6
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		incomplete
        	ViewName:		prim
        	Master Cell Name:	incomplete
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I7
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		busLeaf
        	ViewName:		prim
        	Master Cell Name:	busLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I9
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		busLeaf
        	ViewName:		prim
        	Master Cell Name:	busLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I10
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		busLeaf2
        	ViewName:		prim
        	Master Cell Name:	busLeaf2
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I11
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		noTop
        	ViewName:		prim
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I12
        	LibName:		oaVerilogInTestLeafLib
        	CellName:		blackBox3
        	ViewName:		abstract
        	Master Cell Name:	blackBox3
        	NumBits:		1
        ModInstTerm:
        	Net:	a
        	Inst:	I12
        	Term:	in (not bound)
        ModInstTerm:
        	Net:	a
        	Inst:	I11
        	Term:	in (bound to 'in')
        ModInstTerm:
        	Net:	a
        	Inst:	I6
	Posit:	0 (bound to 'in')
        ModInstTerm:
        	Net:	a
        	Inst:	I5
	Posit:	0 (bound to 'in')
        ModInstTerm:
        	Net:	a
        	Inst:	I4
	Posit:	0 (bound to 'in')
        ModInstTerm:
        	Net:	a
        	Inst:	I3
	Posit:	0 (bound to 'in')
        ModInstTerm:
        	Net:	a
        	Inst:	I2
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	a
        	Inst:	I1
	Posit:	0 (bound to 'in')
        ModInstTerm:
        	Net:	b
        	Inst:	I12
        	Term:	out (not bound)
        ModInstTerm:
        	Net:	b
        	Inst:	I11
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	b
        	Inst:	I6
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	b
        	Inst:	I5
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	b
        	Inst:	I4
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	b
        	Inst:	I3
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	b
        	Inst:	I2
        	Term:	in (bound to 'in')
        ModInstTerm:
        	Net:	b
        	Inst:	I1
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	c
        	Inst:	I6
	Posit:	2 (bound to 'aux')
        ModInstTerm:
        	Net:	x[0:1]
        	Inst:	I10
	Posit:	0 (bound to 'Q[1:0]')
        ModInstTerm:
        	Net:	x[0:1]
        	Inst:	I7
        	Term:	Q[1:0] (not bound)
        ModInstTerm:
        	Net:	n1,n2
        	Inst:	I9
        	Term:	Q[1:0] (not bound)



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Warning: No master module for instances of "oaVerilogInTestLeafLib.noTop.prim" the module will not be produced
// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module scalarLeaf (
    in,
    out);

    input in;
    output out;

endmodule // scalarLeaf


module noOrder (
    .in(x),
    .out(y));

    input x;
    output y;

    wire in;
    wire out;
endmodule // noOrder


module blackBox1 (
    in,
    out);

    input in;
    output out;

endmodule // blackBox1


module blackBox2 (
    .in(x),
    .out(y));

    input x;
    output y;

endmodule // blackBox2


module incomplete (
    in,
    out,
    aux);

    input in;
    output out;
    inout aux;

endmodule // incomplete


module busLeaf (
    Q[1],
    Q[0]);

    inout [1:0] Q;

endmodule // busLeaf


module busLeaf2 (
    Q);

    inout [1:0] Q;

endmodule // busLeaf2


module blackBox3 ();
endmodule // blackBox3


module top ();

    wire a;
    wire b;
    wire c;
    wire [0:1] x;
    wire n1;
    wire n2;

    scalarLeaf I1 (
            .in(a),
            .out(b));
    scalarLeaf I2 (
            .in(b),
            .out(a));
    noOrder I3 (
            .in(a),
            .out(b));
    blackBox1 I4 (
            .in(a),
            .out(b));
    blackBox2 I5 (
            .in(a),
            .out(b));
    incomplete I6 (
            .in(a),
            .out(b),
            .aux(c));
    busLeaf I7 (
            x[0],
            x[1]);
    busLeaf I9 (
            n1,
            n2);
    busLeaf2 I10 (
            .Q(x));
    noTop I11 (
            .in(a),
            .out(b));
    blackBox3 I12 ();
endmodule // top