📄 ansiports.ref
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******************************************************************************* No Explode, No EMH******************************************************************************Warning: Binary operators are not implementedWarning: Always blocks are not implementedContents of ansiPorts_design.XOR.netlist Contents of TOP module XOR Term: 'out' (ModScalarTerm) TermType: output NumBits: 1 Net: 'out' Position: 0 Term: 'a' (ModScalarTerm) TermType: input NumBits: 1 Net: 'a' Position: 1 Term: 'b' (ModScalarTerm) TermType: input NumBits: 1 Net: 'b' Position: 2 Net: 'out' (ModScalarNet) Net: 'a' (ModScalarNet) Net: 'b' (ModScalarNet)Contents of ansiPorts_design.top.netlist Contents of TOP module top Term: 'xout[1:8]' (ModBusTerm) TermType: output NumBits: 8 Net: 'xout[1:8]' Position: 0 Term: 'xin1[1:8]' (ModBusTerm) TermType: input NumBits: 8 Net: 'xin1[1:8]' Position: 1 Term: 'xin2[1:8]' (ModBusTerm) TermType: input NumBits: 8 Net: 'xin2[1:8]' Position: 2 Net: 'xout[1:8]' (ModBusNet) Net: 'xout[1]' (ModBusNetBit) Net: 'xout[2]' (ModBusNetBit) Net: 'xout[3]' (ModBusNetBit) Net: 'xout[4]' (ModBusNetBit) Net: 'xout[5]' (ModBusNetBit) Net: 'xout[6]' (ModBusNetBit) Net: 'xout[7]' (ModBusNetBit) Net: 'xout[8]' (ModBusNetBit) Net: 'xin1[1:8]' (ModBusNet) Net: 'xin1[1]' (ModBusNetBit) Net: 'xin1[2]' (ModBusNetBit) Net: 'xin1[3]' (ModBusNetBit) Net: 'xin1[4]' (ModBusNetBit) Net: 'xin1[5]' (ModBusNetBit) Net: 'xin1[6]' (ModBusNetBit) Net: 'xin1[7]' (ModBusNetBit) Net: 'xin1[8]' (ModBusNetBit) Net: 'xin2[1:8]' (ModBusNet) Net: 'xin2[1]' (ModBusNetBit) Net: 'xin2[2]' (ModBusNetBit) Net: 'xin2[3]' (ModBusNetBit) Net: 'xin2[4]' (ModBusNetBit) Net: 'xin2[5]' (ModBusNetBit) Net: 'xin2[6]' (ModBusNetBit) Net: 'xin2[7]' (ModBusNetBit) Net: 'xin2[8]' (ModBusNetBit) ModInst: Is Bound: yes InstName: a LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: b LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: c LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: d LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: e LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: f LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: g LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: h LibName: ansiPorts_design CellName: XOR ViewName: netlist Master Cell Name: XOR NumBits: 1 ModInstTerm: Net: xout[1] Inst: h Posit: 0 (bound to 'out') ModInstTerm: Net: xout[2] Inst: g Posit: 0 (bound to 'out') ModInstTerm: Net: xout[3] Inst: f Posit: 0 (bound to 'out') ModInstTerm: Net: xout[4] Inst: e Posit: 0 (bound to 'out') ModInstTerm: Net: xout[5] Inst: d Posit: 0 (bound to 'out') ModInstTerm: Net: xout[6] Inst: c Posit: 0 (bound to 'out') ModInstTerm: Net: xout[7] Inst: b Posit: 0 (bound to 'out') ModInstTerm: Net: xout[8] Inst: a Posit: 0 (bound to 'out') ModInstTerm: Net: xin1[1] Inst: h Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[2] Inst: g Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[3] Inst: f Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[4] Inst: e Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[5] Inst: d Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[6] Inst: c Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[7] Inst: b Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[8] Inst: a Posit: 1 (bound to 'a') ModInstTerm: Net: xin2[1] Inst: h Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[2] Inst: g Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[3] Inst: f Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[4] Inst: e Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[5] Inst: d Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[6] Inst: c Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[7] Inst: b Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[8] Inst: a Posit: 2 (bound to 'b')Reader succeeded******************************************************************************* No Explode, EMH******************************************************************************Warning: Binary operators are not implementedWarning: Always blocks are not implementedInfo: The top module is topContents of ansiPorts_designEMH.top.netlist Contents of module XOR Term: 'b' (ModScalarTerm) TermType: input NumBits: 1 Net: 'b' Position: 2 Term: 'a' (ModScalarTerm) TermType: input NumBits: 1 Net: 'a' Position: 1 Term: 'out' (ModScalarTerm) TermType: output NumBits: 1 Net: 'out' Position: 0 Net: 'b' (ModScalarNet) Net: 'a' (ModScalarNet) Net: 'out' (ModScalarNet) Contents of TOP module top Term: 'xin2[1:8]' (ModBusTerm) TermType: input NumBits: 8 Net: 'xin2[1:8]' Position: 2 Term: 'xin1[1:8]' (ModBusTerm) TermType: input NumBits: 8 Net: 'xin1[1:8]' Position: 1 Term: 'xout[1:8]' (ModBusTerm) TermType: output NumBits: 8 Net: 'xout[1:8]' Position: 0 Net: 'xin2[8]' (ModBusNetBit) Net: 'xin2[7]' (ModBusNetBit) Net: 'xin2[6]' (ModBusNetBit) Net: 'xin2[5]' (ModBusNetBit) Net: 'xin2[4]' (ModBusNetBit) Net: 'xin2[3]' (ModBusNetBit) Net: 'xin2[2]' (ModBusNetBit) Net: 'xin2[1]' (ModBusNetBit) Net: 'xin2[1:8]' (ModBusNet) Net: 'xin1[8]' (ModBusNetBit) Net: 'xin1[7]' (ModBusNetBit) Net: 'xin1[6]' (ModBusNetBit) Net: 'xin1[5]' (ModBusNetBit) Net: 'xin1[4]' (ModBusNetBit) Net: 'xin1[3]' (ModBusNetBit) Net: 'xin1[2]' (ModBusNetBit) Net: 'xin1[1]' (ModBusNetBit) Net: 'xin1[1:8]' (ModBusNet) Net: 'xout[8]' (ModBusNetBit) Net: 'xout[7]' (ModBusNetBit) Net: 'xout[6]' (ModBusNetBit) Net: 'xout[5]' (ModBusNetBit) Net: 'xout[4]' (ModBusNetBit) Net: 'xout[3]' (ModBusNetBit) Net: 'xout[2]' (ModBusNetBit) Net: 'xout[1]' (ModBusNetBit) Net: 'xout[1:8]' (ModBusNet) ModInst: Is Bound: yes InstName: h Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: g Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: f Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: e Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: d Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: c Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: b Master Cell Name: XOR NumBits: 1 ModInst: Is Bound: yes InstName: a Master Cell Name: XOR NumBits: 1 ModInstTerm: Net: xin2[8] Inst: a Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[7] Inst: b Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[6] Inst: c Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[5] Inst: d Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[4] Inst: e Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[3] Inst: f Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[2] Inst: g Posit: 2 (bound to 'b') ModInstTerm: Net: xin2[1] Inst: h Posit: 2 (bound to 'b') ModInstTerm: Net: xin1[8] Inst: a Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[7] Inst: b Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[6] Inst: c Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[5] Inst: d Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[4] Inst: e Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[3] Inst: f Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[2] Inst: g Posit: 1 (bound to 'a') ModInstTerm: Net: xin1[1] Inst: h Posit: 1 (bound to 'a') ModInstTerm: Net: xout[8] Inst: a Posit: 0 (bound to 'out') ModInstTerm: Net: xout[7] Inst: b Posit: 0 (bound to 'out') ModInstTerm: Net: xout[6] Inst: c Posit: 0 (bound to 'out') ModInstTerm: Net: xout[5] Inst: d Posit: 0 (bound to 'out') ModInstTerm: Net: xout[4] Inst: e Posit: 0 (bound to 'out') ModInstTerm: Net: xout[3] Inst: f Posit: 0 (bound to 'out') ModInstTerm: Net: xout[2] Inst: g Posit: 0 (bound to 'out') ModInstTerm: Net: xout[1] Inst: h Posit: 0 (bound to 'out')Reader succeeded⌨️ 快捷键说明
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