param.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Warning: Binary operators are not implemented
Contents of param_design.xorx.netlist
    Contents of TOP module xorx
            Term: 'out[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'out[3:0]'
        	Position:	0
            Term: 'in1[3:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	4
        	Net:		'in1[3:0]'
        	Position:	1
            Term: 'in2[3:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	4
        	Net:		'in2[3:0]'
        	Position:	2
            Net: 'out[3:0]' (ModBusNet)
            Net: 'in1[3:0]' (ModBusNet)
            Net: 'in2[3:0]' (ModBusNet)
            Net: 'xin1' (ModScalarNet)



Contents of param_design.top.netlist
    Contents of TOP module top
            Term: 'a1[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'a1[3:0]'
        	Position:	0
            Term: 'a2[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'a2[3:0]'
        	Position:	1
            Net: 'a1[3:0]' (ModBusNet)
            Net: 'a2[3:0]' (ModBusNet)
            Net: 'b1[3:0]' (ModBusNet)
            Net: 'c1[3:0]' (ModBusNet)
            Net: 'b2[3:0]' (ModBusNet)
            Net: 'c2[3:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		a
        	LibName:		param_design
        	CellName:		xorx
        	ViewName:		netlist
        	Master Cell Name:	xorx
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		b
        	LibName:		param_design
        	CellName:		xorx
        	ViewName:		netlist
        	Master Cell Name:	xorx
        	NumBits:		1
        ModInstTerm:
        	Net:	a1[3:0]
        	Inst:	a
	Posit:	0 (bound to 'out[3:0]')
        ModInstTerm:
        	Net:	a2[3:0]
        	Inst:	b
	Posit:	0 (bound to 'out[3:0]')
        ModInstTerm:
        	Net:	b1[3:0]
        	Inst:	a
	Posit:	1 (bound to 'in1[3:0]')
        ModInstTerm:
        	Net:	c1[3:0]
        	Inst:	a
	Posit:	2 (bound to 'in2[3:0]')
        ModInstTerm:
        	Net:	b2[3:0]
        	Inst:	b
	Posit:	1 (bound to 'in1[3:0]')
        ModInstTerm:
        	Net:	c2[3:0]
        	Inst:	b
	Posit:	2 (bound to 'in2[3:0]')



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Warning: Binary operators are not implemented
Info: The top module is top
Contents of param_designEMH.top.netlist
    Contents of module xorx
            Term: 'in2[3:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	4
        	Net:		'in2[3:0]'
        	Position:	2
            Term: 'in1[3:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	4
        	Net:		'in1[3:0]'
        	Position:	1
            Term: 'out[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'out[3:0]'
        	Position:	0
            Net: 'xin1' (ModScalarNet)
            Net: 'in2[3:0]' (ModBusNet)
            Net: 'in1[3:0]' (ModBusNet)
            Net: 'out[3:0]' (ModBusNet)
    Contents of TOP module top
            Term: 'a2[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'a2[3:0]'
        	Position:	1
            Term: 'a1[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'a1[3:0]'
        	Position:	0
            Net: 'c2[3:0]' (ModBusNet)
            Net: 'b2[3:0]' (ModBusNet)
            Net: 'c1[3:0]' (ModBusNet)
            Net: 'b1[3:0]' (ModBusNet)
            Net: 'a2[3:0]' (ModBusNet)
            Net: 'a1[3:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		b
        	Master Cell Name:	xorx
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		a
        	Master Cell Name:	xorx
        	NumBits:		1
        ModInstTerm:
        	Net:	c2[3:0]
        	Inst:	b
	Posit:	2 (bound to 'in2[3:0]')
        ModInstTerm:
        	Net:	b2[3:0]
        	Inst:	b
	Posit:	1 (bound to 'in1[3:0]')
        ModInstTerm:
        	Net:	c1[3:0]
        	Inst:	a
	Posit:	2 (bound to 'in2[3:0]')
        ModInstTerm:
        	Net:	b1[3:0]
        	Inst:	a
	Posit:	1 (bound to 'in1[3:0]')
        ModInstTerm:
        	Net:	a2[3:0]
        	Inst:	b
	Posit:	0 (bound to 'out[3:0]')
        ModInstTerm:
        	Net:	a1[3:0]
        	Inst:	a
	Posit:	0 (bound to 'out[3:0]')



Reader succeeded