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📄 forward.ref

📁 openaccess与verilog互相转化时所用的源代码
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******************************************************************************* No Explode, No EMH******************************************************************************Contents of forward_design.top.netlist    Contents of TOP module top            Net: 'a' (ModScalarNet)            Net: 'b' (ModScalarNet)            Net: 'c' (ModScalarNet)            Net: 'd[1:0]' (ModBusNet)            Net: 'e[1:0]' (ModBusNet)        ModInst:        	Is Bound:		no        	InstName:		named        	LibName:		forward_design        	CellName:		mid        	ViewName:		abstract        	NumBits:		1        ModInst:        	Is Bound:		no        	InstName:		order        	LibName:		forward_design        	CellName:		mid        	ViewName:		abstract        	NumBits:		1        ModInstTerm:        	Net:	a        	Inst:	order	Posit:	0 (not bound)        ModInstTerm:        	Net:	a        	Inst:	named        	Term:	v (not bound)        ModInstTerm:        	Net:	b        	Inst:	order	Posit:	1 (not bound)        ModInstTerm:        	Net:	b        	Inst:	named        	Term:	w (not bound)        ModInstTerm:        	Net:	c        	Inst:	order	Posit:	2 (not bound)        ModInstTerm:        	Net:	c        	Inst:	named        	Term:	x (not bound)        ModInstTerm:        	Net:	d[1:0]        	Inst:	order	Posit:	3 (not bound)        ModInstTerm:        	Net:	d[1:0]        	Inst:	named        	Term:	y[1:0] (not bound)        ModInstTerm:        	Net:	e[1:0]        	Inst:	order	Posit:	4 (not bound)        ModInstTerm:        	Net:	e[1:0]        	Inst:	named        	Term:	z[1:0] (not bound)Contents of forward_design.top.netlist    Contents of TOP module top            Net: 'a' (ModScalarNet)            Net: 'b' (ModScalarNet)            Net: 'c' (ModScalarNet)            Net: 'd[1:0]' (ModBusNet)            Net: 'e[1:0]' (ModBusNet)        ModInst:        	Is Bound:		yes        	InstName:		named        	LibName:		forward_design        	CellName:		mid        	ViewName:		netlist        	Master Cell Name:	mid        	NumBits:		1        ModInst:        	Is Bound:		yes        	InstName:		order        	LibName:		forward_design        	CellName:		mid        	ViewName:		netlist        	Master Cell Name:	mid        	NumBits:		1        ModInstTerm:        	Net:	a        	Inst:	order	Posit:	0 (bound to 'v')        ModInstTerm:        	Net:	a        	Inst:	named        	Term:	v (bound to 'v')        ModInstTerm:        	Net:	b        	Inst:	order	Posit:	1 (bound to 'w')        ModInstTerm:        	Net:	b        	Inst:	named        	Term:	w (bound to 'w')        ModInstTerm:        	Net:	c        	Inst:	order	Posit:	2 (bound to 'x')        ModInstTerm:        	Net:	c        	Inst:	named        	Term:	x (bound to 'x')        ModInstTerm:        	Net:	d[1:0]        	Inst:	order	Posit:	3 (bound to 'y[1:0]')        ModInstTerm:        	Net:	d[1:0]        	Inst:	named        	Term:	y[1:0] (bound to 'y[1:0]')        ModInstTerm:        	Net:	e[1:0]        	Inst:	named        	Term:	z[1:2] (bound to 'z[1:2]')        ModInstTerm:        	Net:	e[1:0]        	Inst:	order	Posit:	4 (bound to 'z[1:2]')Contents of forward_design.mid.netlist    Contents of TOP module mid            Term: 'v' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'v'        	Position:	0            Term: 'w' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'w'        	Position:	1            Term: 'x' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'x'        	Position:	2            Term: 'y[1:0]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'y[1:0]'        	Position:	3            Term: 'z[1:2]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'z[1:2]'        	Position:	4            Net: 'v' (ModScalarNet)            Net: 'w' (ModScalarNet)            Net: 'x' (ModScalarNet)            Net: 'y[1:0]' (ModBusNet)            Net: 'z[1:2]' (ModBusNet)            Net: 'a' (ModScalarNet)            Net: 'b' (ModScalarNet)            Net: 'c' (ModScalarNet)            Net: 'd[3:0]' (ModBusNet)            Net: 'e[3:0]' (ModBusNet)            Net: '2*a' (ModBundleNet)            Net: '2*b' (ModBundleNet)            Net: '2*c' (ModBundleNet)        ModInst:        	Is Bound:		no        	InstName:		order[1:0]        	LibName:		forward_design        	CellName:		bottom        	ViewName:		abstract        	NumBits:		2        ModInst:        	Is Bound:		no        	InstName:		named[1:0]        	LibName:		forward_design        	CellName:		bottom        	ViewName:		abstract        	NumBits:		2        ModInstTerm:        	Net:	d[3:0]        	Inst:	named[1:0]        	Term:	y[1:0] (not bound)        ModInstTerm:        	Net:	d[3:0]        	Inst:	order[1:0]	Posit:	3 (not bound)        ModInstTerm:        	Net:	e[3:0]        	Inst:	named[1:0]        	Term:	z[1:0] (not bound)        ModInstTerm:        	Net:	e[3:0]        	Inst:	order[1:0]	Posit:	4 (not bound)        ModInstTerm:        	Net:	2*a        	Inst:	named[1:0]        	Term:	v (not bound)        ModInstTerm:        	Net:	2*a        	Inst:	order[1:0]	Posit:	0 (not bound)        ModInstTerm:        	Net:	2*b        	Inst:	named[1:0]        	Term:	w (not bound)        ModInstTerm:        	Net:	2*b        	Inst:	order[1:0]	Posit:	1 (not bound)        ModInstTerm:        	Net:	2*c        	Inst:	named[1:0]        	Term:	x (not bound)        ModInstTerm:        	Net:	2*c        	Inst:	order[1:0]	Posit:	2 (not bound)Contents of forward_design.mid.netlist    Contents of TOP module mid            Term: 'v' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'v'        	Position:	0            Term: 'w' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'w'        	Position:	1            Term: 'x' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'x'        	Position:	2            Term: 'y[1:0]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'y[1:0]'        	Position:	3            Term: 'z[1:2]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'z[1:2]'        	Position:	4            Net: 'v' (ModScalarNet)            Net: 'w' (ModScalarNet)            Net: 'x' (ModScalarNet)            Net: 'y[1:0]' (ModBusNet)            Net: 'z[1:2]' (ModBusNet)            Net: 'a' (ModScalarNet)            Net: 'b' (ModScalarNet)            Net: 'c' (ModScalarNet)            Net: 'd[3:0]' (ModBusNet)            Net: 'e[3:0]' (ModBusNet)            Net: '2*a' (ModBundleNet)            Net: '2*b' (ModBundleNet)            Net: '2*c' (ModBundleNet)        ModInst:        	Is Bound:		yes        	InstName:		order[1:0]        	LibName:		forward_design        	CellName:		bottom        	ViewName:		netlist        	Master Cell Name:	bottom        	NumBits:		2        ModInst:        	Is Bound:		yes        	InstName:		named[1:0]        	LibName:		forward_design        	CellName:		bottom        	ViewName:		netlist        	Master Cell Name:	bottom        	NumBits:		2        ModInstTerm:        	Net:	d[3:0]        	Inst:	named[1:0]        	Term:	y[1:0] (bound to 'y[1:0]')        ModInstTerm:        	Net:	d[3:0]        	Inst:	order[1:0]	Posit:	3 (bound to 'y[1:0]')        ModInstTerm:        	Net:	e[3:0]        	Inst:	named[1:0]        	Term:	z[1:0] (bound to 'z[1:0]')        ModInstTerm:        	Net:	e[3:0]        	Inst:	order[1:0]	Posit:	4 (bound to 'z[1:0]')        ModInstTerm:        	Net:	2*a        	Inst:	named[1:0]        	Term:	v (bound to 'v')        ModInstTerm:        	Net:	2*a        	Inst:	order[1:0]	Posit:	0 (bound to 'v')        ModInstTerm:        	Net:	2*b        	Inst:	named[1:0]        	Term:	w (bound to 'w')        ModInstTerm:        	Net:	2*b        	Inst:	order[1:0]	Posit:	1 (bound to 'w')        ModInstTerm:        	Net:	2*c        	Inst:	named[1:0]        	Term:	x (bound to 'x')        ModInstTerm:        	Net:	2*c        	Inst:	order[1:0]	Posit:	2 (bound to 'x')Contents of forward_design.bottom.netlist    Contents of TOP module bottom            Term: 'v' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'v'        	Position:	0            Term: 'w' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'w'        	Position:	1            Term: 'x' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'x'        	Position:	2            Term: 'y[1:0]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'y[1:0]'        	Position:	3            Term: 'z[1:0]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'z[1:0]'        	Position:	4            Net: 'v' (ModScalarNet)            Net: 'w' (ModScalarNet)            Net: 'x' (ModScalarNet)            Net: 'y[1:0]' (ModBusNet)            Net: 'z[1:0]' (ModBusNet)Reader succeeded******************************************************************************* No Explode, EMH******************************************************************************Info: The top module is topContents of forward_designEMH.top.netlist    Contents of TOP module top            Net: 'e[1:0]' (ModBusNet)            Net: 'd[1:0]' (ModBusNet)            Net: 'c' (ModScalarNet)            Net: 'b' (ModScalarNet)            Net: 'a' (ModScalarNet)        ModInst:        	Is Bound:		yes        	InstName:		order        	Master Cell Name:	mid        	NumBits:		1        ModInst:        	Is Bound:		yes        	InstName:		named        	Master Cell Name:	mid        	NumBits:		1        ModInstTerm:        	Net:	e[1:0]        	Inst:	named        	Term:	z[1:2] (bound to 'z[1:2]')        ModInstTerm:        	Net:	e[1:0]        	Inst:	order	Posit:	4 (bound to 'z[1:2]')        ModInstTerm:        	Net:	d[1:0]        	Inst:	order	Posit:	3 (bound to 'y[1:0]')        ModInstTerm:        	Net:	d[1:0]        	Inst:	named        	Term:	y[1:0] (bound to 'y[1:0]')        ModInstTerm:        	Net:	c        	Inst:	order	Posit:	2 (bound to 'x')        ModInstTerm:        	Net:	c        	Inst:	named        	Term:	x (bound to 'x')        ModInstTerm:        	Net:	b        	Inst:	order	Posit:	1 (bound to 'w')        ModInstTerm:        	Net:	b        	Inst:	named        	Term:	w (bound to 'w')        ModInstTerm:        	Net:	a        	Inst:	order	Posit:	0 (bound to 'v')        ModInstTerm:        	Net:	a        	Inst:	named        	Term:	v (bound to 'v')    Contents of module mid            Term: 'z[1:2]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'z[1:2]'        	Position:	4            Term: 'y[1:0]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'y[1:0]'        	Position:	3            Term: 'x' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'x'        	Position:	2            Term: 'w' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'w'        	Position:	1            Term: 'v' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'v'        	Position:	0            Net: '2*c' (ModBundleNet)            Net: '2*b' (ModBundleNet)            Net: '2*a' (ModBundleNet)            Net: 'e[3:0]' (ModBusNet)            Net: 'd[3:0]' (ModBusNet)            Net: 'c' (ModScalarNet)            Net: 'b' (ModScalarNet)            Net: 'a' (ModScalarNet)            Net: 'z[1:2]' (ModBusNet)            Net: 'y[1:0]' (ModBusNet)            Net: 'x' (ModScalarNet)            Net: 'w' (ModScalarNet)            Net: 'v' (ModScalarNet)        ModInst:        	Is Bound:		yes        	InstName:		named[1:0]        	Master Cell Name:	bottom        	NumBits:		2        ModInst:        	Is Bound:		yes        	InstName:		order[1:0]        	Master Cell Name:	bottom        	NumBits:		2        ModInstTerm:        	Net:	2*c        	Inst:	named[1:0]        	Term:	x (bound to 'x')        ModInstTerm:        	Net:	2*c        	Inst:	order[1:0]	Posit:	2 (bound to 'x')        ModInstTerm:        	Net:	2*b        	Inst:	named[1:0]        	Term:	w (bound to 'w')        ModInstTerm:        	Net:	2*b        	Inst:	order[1:0]	Posit:	1 (bound to 'w')        ModInstTerm:        	Net:	2*a        	Inst:	named[1:0]        	Term:	v (bound to 'v')        ModInstTerm:        	Net:	2*a        	Inst:	order[1:0]	Posit:	0 (bound to 'v')        ModInstTerm:        	Net:	e[3:0]        	Inst:	named[1:0]        	Term:	z[1:0] (bound to 'z[1:0]')        ModInstTerm:        	Net:	e[3:0]        	Inst:	order[1:0]	Posit:	4 (bound to 'z[1:0]')        ModInstTerm:        	Net:	d[3:0]        	Inst:	named[1:0]        	Term:	y[1:0] (bound to 'y[1:0]')        ModInstTerm:        	Net:	d[3:0]        	Inst:	order[1:0]	Posit:	3 (bound to 'y[1:0]')    Contents of module bottom            Term: 'z[1:0]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'z[1:0]'        	Position:	4            Term: 'y[1:0]' (ModBusTerm)        	TermType:	inputOutput        	NumBits:	2        	Net:		'y[1:0]'        	Position:	3            Term: 'x' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'x'        	Position:	2            Term: 'w' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'w'        	Position:	1            Term: 'v' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'v'        	Position:	0            Net: 'z[1:0]' (ModBusNet)            Net: 'y[1:0]' (ModBusNet)            Net: 'x' (ModScalarNet)            Net: 'w' (ModScalarNet)            Net: 'v' (ModScalarNet)Reader succeeded

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