代码搜索：Numeric
找到约 7,754 项符合「Numeric」的源代码
代码结果 7,754
www.eeworm.com/read/403922/11504097
html function.mb-decode-numericentity.html
Decode HTML numeric string reference to character
www.eeworm.com/read/403922/11504649
html function.mb-encode-numericentity.html
Encode character to HTML numeric string reference
www.eeworm.com/read/341971/12052372
vhd svpwm_top_tb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY svpwm_top_tb IS
END svpwm_top_tb;
ARCHITECTURE behavior OF svpwm_top_tb IS
C
www.eeworm.com/read/341658/12074389
vhd out_mux.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic;
use basic.mnemonics.all;
entity out_mux is port(
ad,f:in unsigned(3 downto 0);
dest_ctl:in std_lo
www.eeworm.com/read/341658/12074391
vhd src_op.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic;
use basic.mnemonics.all;
entity src_op is port(
src_ctl:in std_logic_vector(2 downto 0);
d,ad
www.eeworm.com/read/233403/14154957
vhd sinetest4ksample1ksignal.vhd
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity SineTest4KSample1KSignal is
end entity SineTest4KSample1KSignal;
architecture OneK
www.eeworm.com/read/116130/14987788
vhd pbch.vhd
-- VHDL model created from schematic pbch.sch -- Feb 27 12:02:14 2002
LIBRARY ieee;
LIBRARY generics;
LIBRARY lat_vhd;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.compo
www.eeworm.com/read/210234/15203152
vhf pingche.vhf
-- VHDL model created from pingche.sch - Sat Mar 24 20:54:01 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vc
www.eeworm.com/read/210234/15203255
vhf jsq.vhf
-- VHDL model created from jsq.sch - Fri Mar 16 08:33:17 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcompo
www.eeworm.com/read/210233/15203460
vhf qd.vhf
-- VHDL model created from qd.sch - Tue Apr 24 08:18:20 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcompon