📄 pbch.vhd
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-- VHDL model created from schematic pbch.sch -- Feb 27 12:02:14 2002
LIBRARY ieee;
LIBRARY generics;
LIBRARY lat_vhd;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;
USE lat_vhd.vhd_pkg.ALL;
entity PBCH is
Port ( CLK : In std_logic;
CLR : In std_logic;
KEY : In std_logic;
a : Out std_logic;
b : Out std_logic;
c : Out std_logic;
d : Out std_logic;
dt : Out std_logic;
e : Out std_logic;
f : Out std_logic;
g : Out std_logic;
SEG1 : Out std_logic;
SEG2 : Out std_logic;
SEG3 : Out std_logic;
SEG4 : Out std_logic;
SEG5 : Out std_logic;
SEG6 : Out std_logic;
SEG7 : Out std_logic;
SEG8 : Out std_logic );
end PBCH;
architecture SCHEMATIC of PBCH is
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
signal N_49 : std_logic;
signal N_50 : std_logic;
signal N_41 : std_logic;
signal N_42 : std_logic;
signal N_43 : std_logic;
signal N_44 : std_logic;
signal N_45 : std_logic;
signal N_46 : std_logic;
signal N_47 : std_logic;
signal N_48 : std_logic;
signal N_1 : std_logic;
signal N_2 : std_logic;
signal N_3 : std_logic;
signal N_4 : std_logic;
signal N_5 : std_logic;
signal N_6 : std_logic;
signal N_7 : std_logic;
signal N_8 : std_logic;
signal N_9 : std_logic;
signal N_10 : std_logic;
signal N_11 : std_logic;
signal N_12 : std_logic;
signal N_13 : std_logic;
signal N_14 : std_logic;
signal N_15 : std_logic;
signal N_16 : std_logic;
signal N_17 : std_logic;
signal N_18 : std_logic;
signal N_19 : std_logic;
signal N_20 : std_logic;
signal N_21 : std_logic;
signal N_22 : std_logic;
signal N_23 : std_logic;
signal N_24 : std_logic;
signal N_25 : std_logic;
signal N_26 : std_logic;
signal N_27 : std_logic;
signal N_28 : std_logic;
signal N_29 : std_logic;
signal N_30 : std_logic;
signal N_31 : std_logic;
signal N_32 : std_logic;
signal N_33 : std_logic;
signal N_34 : std_logic;
signal N_36 : std_logic;
signal N_37 : std_logic;
signal N_38 : std_logic;
signal N_39 : std_logic;
component CDT10
Port ( CLK : In std_logic;
CLR : In std_logic;
EN : In std_logic;
CY : Out std_logic;
Q0 : Out std_logic;
Q1 : Out std_logic;
Q2 : Out std_logic;
Q3 : Out std_logic );
end component;
component BC07
Port ( D0 : In std_logic;
D1 : In std_logic;
D2 : In std_logic;
D3 : In std_logic;
a : Out std_logic;
b : Out std_logic;
c : Out std_logic;
d : Out std_logic;
dt : Out std_logic;
e : Out std_logic;
f : Out std_logic;
g : Out std_logic );
end component;
component NULX
Port ( CLK : In std_logic;
M0 : In std_logic;
M1 : In std_logic;
M2 : In std_logic;
M3 : In std_logic;
M4 : In std_logic;
M5 : In std_logic;
M6 : In std_logic;
MS0 : In std_logic;
MS1 : In std_logic;
MS2 : In std_logic;
MS3 : In std_logic;
MS4 : In std_logic;
MS5 : In std_logic;
MS6 : In std_logic;
MS7 : In std_logic;
S0 : In std_logic;
S1 : In std_logic;
S2 : In std_logic;
S3 : In std_logic;
S4 : In std_logic;
S5 : In std_logic;
S6 : In std_logic;
OUT0 : Out std_logic;
OUT1 : Out std_logic;
OUT2 : Out std_logic;
OUT3 : Out std_logic;
SEG1 : Out std_logic;
SEG2 : Out std_logic;
SEG3 : Out std_logic;
SEG4 : Out std_logic;
SEG5 : Out std_logic;
SEG6 : Out std_logic;
SEG7 : Out std_logic;
SEG8 : Out std_logic );
end component;
component COUT
Port ( CLK : In std_logic;
CLR : In std_logic;
EN : In std_logic;
B0 : Out std_logic;
B1 : Out std_logic;
B2 : Out std_logic;
B3 : Out std_logic;
B4 : Out std_logic;
B5 : Out std_logic;
B6 : Out std_logic;
M0 : Out std_logic;
M1 : Out std_logic;
M2 : Out std_logic;
M3 : Out std_logic;
M4 : Out std_logic;
M5 : Out std_logic;
M6 : Out std_logic;
MB0 : Out std_logic;
MB1 : Out std_logic;
MB2 : Out std_logic;
MB3 : Out std_logic;
MB4 : Out std_logic;
MB5 : Out std_logic;
MB6 : Out std_logic;
MB7 : Out std_logic );
end component;
component KEY
Port ( CLK : In std_logic;
K : In std_logic;
EN : Out std_logic );
end component;
begin
I26 : CDT10
Port Map ( CLK=>N_37, CLR=>GND, EN=>VCC, CY=>open, Q0=>N_36,
Q1=>open, Q2=>open, Q3=>open );
I1 : G_INV
Port Map ( A=>N_39, YN=>N_38 );
I2 : G_OUTPUT
Port Map ( I=>N_41, O=>SEG8 );
I3 : G_OUTPUT
Port Map ( I=>N_42, O=>SEG7 );
I4 : G_OUTPUT
Port Map ( I=>N_43, O=>SEG6 );
I5 : G_OUTPUT
Port Map ( I=>N_44, O=>SEG5 );
I6 : G_OUTPUT
Port Map ( I=>N_45, O=>SEG4 );
I7 : G_OUTPUT
Port Map ( I=>N_46, O=>SEG3 );
I8 : G_OUTPUT
Port Map ( I=>N_47, O=>SEG2 );
I9 : G_OUTPUT
Port Map ( I=>N_48, O=>SEG1 );
I10 : G_OUTPUT
Port Map ( I=>N_1, O=>dt );
I11 : G_OUTPUT
Port Map ( I=>N_2, O=>g );
I12 : G_OUTPUT
Port Map ( I=>N_3, O=>f );
I13 : G_OUTPUT
Port Map ( I=>N_8, O=>e );
I14 : G_OUTPUT
Port Map ( I=>N_7, O=>d );
I15 : G_OUTPUT
Port Map ( I=>N_6, O=>c );
I16 : G_OUTPUT
Port Map ( I=>N_5, O=>b );
I17 : G_OUTPUT
Port Map ( I=>N_4, O=>a );
17 : G_INPUT
Port Map ( I=>KEY, O=>N_50 );
16 : G_INPUT
Port Map ( I=>CLR, O=>N_39 );
15 : G_INPUT
Port Map ( I=>CLK, O=>N_37 );
I21 : BC07
Port Map ( D0=>N_9, D1=>N_10, D2=>N_11, D3=>N_12, a=>N_4, b=>N_5,
c=>N_6, d=>N_7, dt=>N_1, e=>N_8, f=>N_3, g=>N_2 );
I22 : NULX
Port Map ( CLK=>N_37, M0=>N_34, M1=>N_33, M2=>N_32, M3=>N_31,
M4=>N_30, M5=>N_29, M6=>N_28, MS0=>N_20, MS1=>N_19,
MS2=>N_18, MS3=>N_17, MS4=>N_16, MS5=>N_15, MS6=>N_14,
MS7=>N_13, S0=>N_27, S1=>N_26, S2=>N_25, S3=>N_24,
S4=>N_23, S5=>N_22, S6=>N_21, OUT0=>N_9, OUT1=>N_10,
OUT2=>N_11, OUT3=>N_12, SEG1=>N_48, SEG2=>N_47,
SEG3=>N_46, SEG4=>N_45, SEG5=>N_44, SEG6=>N_43,
SEG7=>N_42, SEG8=>N_41 );
I23 : COUT
Port Map ( CLK=>N_36, CLR=>N_38, EN=>N_49, B0=>N_27, B1=>N_26,
B2=>N_25, B3=>N_24, B4=>N_23, B5=>N_22, B6=>N_21,
M0=>N_34, M1=>N_33, M2=>N_32, M3=>N_31, M4=>N_30,
M5=>N_29, M6=>N_28, MB0=>N_20, MB1=>N_19, MB2=>N_18,
MB3=>N_17, MB4=>N_16, MB5=>N_15, MB6=>N_14, MB7=>N_13 );
I25 : KEY
Port Map ( CLK=>N_36, K=>N_50, EN=>N_49 );
end SCHEMATIC;
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