pingche.vhf

简易数字频率计

-- VHDL model created from pingche.sch - Sat Mar 24 20:54:01 2007


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity pingche is
   port ( clk   : in    std_logic; 
          reset : in    std_logic; 
          rst   : in    std_logic; 
          seg   : out   std_logic_vector (6 downto 0); 
          wx    : out   std_logic_vector (2 downto 0));
end pingche;

architecture BEHAVIORAL of pingche is
   attribute BOX_TYPE   : STRING ;
   signal XLXN_1   : std_logic;
   signal XLXN_3   : std_logic_vector (3 downto 0);
   signal XLXN_4   : std_logic_vector (3 downto 0);
   signal XLXN_5   : std_logic_vector (3 downto 0);
   signal XLXN_6   : std_logic_vector (3 downto 0);
   signal XLXN_7   : std_logic_vector (3 downto 0);
   signal XLXN_8   : std_logic_vector (3 downto 0);
   signal XLXN_9   : std_logic_vector (3 downto 0);
   signal XLXN_10  : std_logic_vector (3 downto 0);
   signal XLXN_11  : std_logic_vector (3 downto 0);
   signal XLXN_12  : std_logic_vector (3 downto 0);
   signal XLXN_13  : std_logic_vector (3 downto 0);
   signal XLXN_14  : std_logic_vector (3 downto 0);
   signal XLXN_16  : std_logic;
   signal XLXN_17  : std_logic;
   signal XLXN_18  : std_logic;
   signal XLXN_21  : std_logic_vector (3 downto 0);
   signal XLXN_22  : std_logic;
   signal XLXN_23  : std_logic;
   signal XLXN_24  : std_logic;
   signal XLXN_25  : std_logic;
   signal wx_DUMMY : std_logic_vector (2 downto 0);
   component fpq1s
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component fpq2ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component jsq
      port ( clk : in    std_logic; 
             en  : in    std_logic; 
             clr : in    std_logic; 
             q1  : out   std_logic_vector (3 downto 0); 
             q2  : out   std_logic_vector (3 downto 0); 
             q3  : out   std_logic_vector (3 downto 0); 
             q4  : out   std_logic_vector (3 downto 0); 
             q5  : out   std_logic_vector (3 downto 0); 
             q6  : out   std_logic_vector (3 downto 0));
   end component;
   
   component s_6
      port ( CP : in    std_logic; 
             s  : out   std_logic_vector (2 downto 0));
   end component;
   
   component scq
      port ( LOAD : in    std_logic; 
             D1   : in    std_logic_vector (3 downto 0); 
             D2   : in    std_logic_vector (3 downto 0); 
             D3   : in    std_logic_vector (3 downto 0); 
             D4   : in    std_logic_vector (3 downto 0); 
             D5   : in    std_logic_vector (3 downto 0); 
             D6   : in    std_logic_vector (3 downto 0); 
             Q1   : inout std_logic_vector (3 downto 0); 
             Q2   : inout std_logic_vector (3 downto 0); 
             Q3   : inout std_logic_vector (3 downto 0); 
             Q4   : inout std_logic_vector (3 downto 0); 
             Q5   : inout std_logic_vector (3 downto 0); 
             Q6   : inout std_logic_vector (3 downto 0));
   end component;
   
   component szq
      port ( Q1 : in    std_logic_vector (3 downto 0); 
             Q2 : in    std_logic_vector (3 downto 0); 
             Q3 : in    std_logic_vector (3 downto 0); 
             Q4 : in    std_logic_vector (3 downto 0); 
             Q5 : in    std_logic_vector (3 downto 0); 
             Q6 : in    std_logic_vector (3 downto 0); 
             S  : in    std_logic_vector (2 downto 0); 
             Q  : out   std_logic_vector (3 downto 0));
   end component;
   
   component ymq
      port ( A : in    std_logic_vector (3 downto 0); 
             Q : out   std_logic_vector (6 downto 0));
   end component;
   
   component kz2
      port ( CP         : in    std_logic; 
             RST        : in    std_logic; 
             COUNT_EN   : out   std_logic; 
             COUNT_CLR  : out   std_logic; 
             COUNT_LOAD : out   std_logic);
   end component;
   
   component div5freq
      port ( clk    : in    std_logic; 
             rst    : in    std_logic; 
             clk4v1 : out   std_logic; 
             clk1v1 : out   std_logic);
   end component;
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : COMPONENT is "BLACK_BOX";
   
begin
   wx(2 downto 0) <= wx_DUMMY(2 downto 0);
   XLXI_1 : fpq1s
      port map (CLK=>clk, CP=>XLXN_1);
   
   XLXI_2 : fpq2ms
      port map (CLK=>clk, CP=>XLXN_22);
   
   XLXI_3 : jsq
      port map (clk=>XLXN_25, clr=>XLXN_16, en=>XLXN_17, q1(3 downto
            0)=>XLXN_3(3 downto 0), q2(3 downto 0)=>XLXN_4(3 downto 0), q3(3
            downto 0)=>XLXN_5(3 downto 0), q4(3 downto 0)=>XLXN_6(3 downto 0),
            q5(3 downto 0)=>XLXN_7(3 downto 0), q6(3 downto 0)=>XLXN_8(3 downto
            0));
   
   XLXI_5 : s_6
      port map (CP=>XLXN_22, s(2 downto 0)=>wx_DUMMY(2 downto 0));
   
   XLXI_6 : scq
      port map (D1(3 downto 0)=>XLXN_3(3 downto 0), D2(3 downto 0)=>XLXN_4(3
            downto 0), D3(3 downto 0)=>XLXN_5(3 downto 0), D4(3 downto
            0)=>XLXN_6(3 downto 0), D5(3 downto 0)=>XLXN_7(3 downto 0), D6(3
            downto 0)=>XLXN_8(3 downto 0), LOAD=>XLXN_18, Q1(3 downto
            0)=>XLXN_9(3 downto 0), Q2(3 downto 0)=>XLXN_10(3 downto 0), Q3(3
            downto 0)=>XLXN_11(3 downto 0), Q4(3 downto 0)=>XLXN_12(3 downto
            0), Q5(3 downto 0)=>XLXN_13(3 downto 0), Q6(3 downto 0)=>XLXN_14(3
            downto 0));
   
   XLXI_7 : szq
      port map (Q1(3 downto 0)=>XLXN_9(3 downto 0), Q2(3 downto 0)=>XLXN_10(3
            downto 0), Q3(3 downto 0)=>XLXN_11(3 downto 0), Q4(3 downto
            0)=>XLXN_12(3 downto 0), Q5(3 downto 0)=>XLXN_13(3 downto 0), Q6(3
            downto 0)=>XLXN_14(3 downto 0), S(2 downto 0)=>wx_DUMMY(2 downto
            0), Q(3 downto 0)=>XLXN_21(3 downto 0));
   
   XLXI_9 : ymq
      port map (A(3 downto 0)=>XLXN_21(3 downto 0), Q(6 downto 0)=>seg(6 downto
            0));
   
   XLXI_10 : kz2
      port map (CP=>XLXN_1, RST=>reset, COUNT_CLR=>XLXN_16, COUNT_EN=>XLXN_17,
            COUNT_LOAD=>XLXN_18);
   
   XLXI_12 : div5freq
      port map (clk=>clk, rst=>rst, clk1v1=>XLXN_24, clk4v1=>XLXN_23);
   
   XLXI_13 : AND2
      port map (I0=>XLXN_24, I1=>XLXN_23, O=>XLXN_25);
   
end BEHAVIORAL;