jsq.vhf

简易数字频率计

-- VHDL model created from jsq.sch - Fri Mar 16 08:33:17 2007


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity jsq is
   port ( clk : in    std_logic; 
          clr : in    std_logic; 
          en  : in    std_logic; 
          q1  : out   std_logic_vector (3 downto 0); 
          q2  : out   std_logic_vector (3 downto 0); 
          q3  : out   std_logic_vector (3 downto 0); 
          q4  : out   std_logic_vector (3 downto 0); 
          q5  : out   std_logic_vector (3 downto 0); 
          q6  : out   std_logic_vector (3 downto 0));
end jsq;

architecture BEHAVIORAL of jsq is
   signal XLXN_1   : std_logic;
   signal XLXN_2   : std_logic;
   signal XLXN_3   : std_logic;
   signal XLXN_4   : std_logic;
   signal XLXN_5   : std_logic;
   signal q1_DUMMY : std_logic_vector (3 downto 0);
   signal q2_DUMMY : std_logic_vector (3 downto 0);
   signal q3_DUMMY : std_logic_vector (3 downto 0);
   signal q4_DUMMY : std_logic_vector (3 downto 0);
   signal q5_DUMMY : std_logic_vector (3 downto 0);
   signal q6_DUMMY : std_logic_vector (3 downto 0);
   component jsq1
      port ( CLK  : in    std_logic; 
             CLR  : in    std_logic; 
             EN   : in    std_logic; 
             COUT : out   std_logic; 
             D1   : inout std_logic_vector (3 downto 0));
   end component;
   
   component jsq2
      port ( CIN  : in    std_logic; 
             CLR  : in    std_logic; 
             COUT : out   std_logic; 
             D2   : inout std_logic_vector (3 downto 0));
   end component;
   
   component jsq3
      port ( CIN  : in    std_logic; 
             CLR  : in    std_logic; 
             COUT : out   std_logic; 
             D3   : inout std_logic_vector (3 downto 0));
   end component;
   
   component jsq4
      port ( CIN  : in    std_logic; 
             CLR  : in    std_logic; 
             COUT : out   std_logic; 
             D4   : inout std_logic_vector (3 downto 0));
   end component;
   
   component jsq5
      port ( CIN  : in    std_logic; 
             CLR  : in    std_logic; 
             COUT : out   std_logic; 
             D5   : inout std_logic_vector (3 downto 0));
   end component;
   
   component jsq6
      port ( CIN : in    std_logic; 
             CLR : in    std_logic; 
             D6  : inout std_logic_vector (3 downto 0));
   end component;
   
begin
   q1(3 downto 0) <= q1_DUMMY(3 downto 0);
   q2(3 downto 0) <= q2_DUMMY(3 downto 0);
   q3(3 downto 0) <= q3_DUMMY(3 downto 0);
   q4(3 downto 0) <= q4_DUMMY(3 downto 0);
   q5(3 downto 0) <= q5_DUMMY(3 downto 0);
   q6(3 downto 0) <= q6_DUMMY(3 downto 0);
   XLXI_1 : jsq1
      port map (CLK=>clk, CLR=>clr, EN=>en, COUT=>XLXN_1, D1(3 downto
            0)=>q1_DUMMY(3 downto 0));
   
   XLXI_2 : jsq2
      port map (CIN=>XLXN_1, CLR=>clr, COUT=>XLXN_2, D2(3 downto 0)=>q2_DUMMY(3
            downto 0));
   
   XLXI_3 : jsq3
      port map (CIN=>XLXN_2, CLR=>clr, COUT=>XLXN_3, D3(3 downto 0)=>q3_DUMMY(3
            downto 0));
   
   XLXI_4 : jsq4
      port map (CIN=>XLXN_3, CLR=>clr, COUT=>XLXN_4, D4(3 downto 0)=>q4_DUMMY(3
            downto 0));
   
   XLXI_5 : jsq5
      port map (CIN=>XLXN_4, CLR=>clr, COUT=>XLXN_5, D5(3 downto 0)=>q5_DUMMY(3
            downto 0));
   
   XLXI_6 : jsq6
      port map (CIN=>XLXN_5, CLR=>clr, D6(3 downto 0)=>q6_DUMMY(3 downto 0));
   
end BEHAVIORAL;