qd.vhf

四人抢答器的实现

-- VHDL model created from qd.sch - Tue Apr 24 08:18:20 2007


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity qd is
   port ( clk   : in    std_logic; 
          clr   : in    std_logic; 
          d1    : in    std_logic; 
          d2    : in    std_logic; 
          d3    : in    std_logic; 
          d4    : in    std_logic; 
          en    : in    std_logic; 
          q     : out   std_logic_vector (7 downto 0); 
          sound : out   std_logic; 
          wx    : out   std_logic_vector (7 downto 0));
end qd;

architecture BEHAVIORAL of qd is
   attribute BOX_TYPE   : STRING ;
   attribute INIT       : STRING ;
   signal XLXN_1   : std_logic;
   signal XLXN_5   : std_logic;
   signal XLXN_6   : std_logic;
   signal XLXN_7   : std_logic;
   signal XLXN_8   : std_logic;
   signal XLXN_9   : std_logic;
   signal XLXN_22  : std_logic;
   signal XLXN_24  : std_logic_vector (3 downto 0);
   signal XLXN_25  : std_logic_vector (3 downto 0);
   signal XLXN_26  : std_logic_vector (3 downto 0);
   signal XLXN_29  : std_logic;
   signal XLXN_30  : std_logic;
   signal XLXN_32  : std_logic;
   signal XLXN_33  : std_logic;
   signal XLXN_34  : std_logic;
   signal XLXN_35  : std_logic;
   signal XLXN_39  : std_logic;
   signal XLXN_48  : std_logic;
   signal XLXN_51  : std_logic;
   signal XLXN_56  : std_logic;
   signal XLXN_57  : std_logic;
   signal XLXN_74  : std_logic_vector (3 downto 0);
   signal wx_DUMMY : std_logic_vector (7 downto 0);
   component ch41a
      port ( d1 : in    std_logic; 
             d2 : in    std_logic; 
             d3 : in    std_logic; 
             d4 : in    std_logic; 
             q  : out   std_logic_vector (3 downto 0));
   end component;
   
   component feng1
      port ( cp  : in    std_logic; 
             clr : in    std_logic; 
             q   : out   std_logic);
   end component;
   
   component fpq1s
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component lock
      port ( d1  : in    std_logic; 
             d2  : in    std_logic; 
             d3  : in    std_logic; 
             d4  : in    std_logic; 
             clk : in    std_logic; 
             clr : in    std_logic; 
             q1  : out   std_logic; 
             q2  : out   std_logic; 
             q3  : out   std_logic; 
             q4  : out   std_logic; 
             alm : out   std_logic);
   end component;
   
   component sel
      port ( clk : in    std_logic; 
             a   : out   std_logic_vector (2 downto 0));
   end component;
   
   component XOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XOR2 : COMPONENT is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : COMPONENT is "BLACK_BOX";
   
   component djs2
      port ( clk   : in    std_logic; 
             en    : in    std_logic; 
             sound : out   std_logic; 
             h     : out   std_logic_vector (3 downto 0); 
             l     : out   std_logic_vector (3 downto 0));
   end component;
   
   component FDCP
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             PRE : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute INIT of FDCP : COMPONENT is "0";
   attribute BOX_TYPE of FDCP : COMPONENT is "BLACK_BOX";
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : COMPONENT is "BLACK_BOX";
   
   component AND4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4 : COMPONENT is "BLACK_BOX";
   
   component NOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of NOR2 : COMPONENT is "BLACK_BOX";
   
   component f01ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component xzq3
      port ( sel : in    std_logic_vector (2 downto 0); 
             d1  : in    std_logic_vector (3 downto 0); 
             d2  : in    std_logic_vector (3 downto 0); 
             d3  : in    std_logic_vector (3 downto 0); 
             wx  : out   std_logic_vector (7 downto 0); 
             q   : out   std_logic_vector (3 downto 0));
   end component;
   
   component ymq
      port ( A : in    std_logic_vector (3 downto 0); 
             Q : out   std_logic_vector (7 downto 0));
   end component;
   
begin
   wx(7 downto 0) <= wx_DUMMY(7 downto 0);
   XLXI_1 : ch41a
      port map (d1=>XLXN_6, d2=>XLXN_7, d3=>XLXN_8, d4=>XLXN_9, q(3 downto
            0)=>XLXN_24(3 downto 0));
   
   XLXI_4 : feng1
      port map (clr=>clr, cp=>XLXN_22, q=>XLXN_5);
   
   XLXI_5 : fpq1s
      port map (CLK=>clk, CP=>XLXN_51);
   
   XLXI_7 : lock
      port map (clk=>XLXN_5, clr=>clr, d1=>d1, d2=>d2, d3=>d3, d4=>d4,
            alm=>XLXN_33, q1=>XLXN_6, q2=>XLXN_7, q3=>XLXN_8, q4=>XLXN_9);
   
   XLXI_8 : sel
      port map (clk=>XLXN_1, a(2 downto 0)=>wx_Dummy(2 downto 0));
   
   XLXI_22 : XOR2
      port map (I0=>XLXN_29, I1=>XLXN_39, O=>XLXN_34);
   
   XLXI_23 : XOR2
      port map (I0=>XLXN_30, I1=>XLXN_33, O=>XLXN_32);
   
   XLXI_24 : AND2
      port map (I0=>XLXN_32, I1=>XLXN_33, O=>XLXN_35);
   
   XLXI_25 : AND2
      port map (I0=>XLXN_34, I1=>XLXN_39, O=>XLXN_48);
   
   XLXI_28 : djs2
      port map (clk=>XLXN_51, en=>en, h(3 downto 0)=>XLXN_25(3 downto 0), l(3
            downto 0)=>XLXN_26(3 downto 0), sound=>XLXN_39);
   
   XLXI_29 : FDCP
      port map (C=>XLXN_51, CLR=>XLXN_56, D=>XLXN_39, PRE=>XLXN_56, Q=>XLXN_29);
   
   XLXI_30 : FDCP
      port map (C=>XLXN_51, CLR=>XLXN_57, D=>XLXN_33, PRE=>XLXN_57, Q=>XLXN_30);
   
   XLXI_31 : VCC
      port map (P=>XLXN_56);
   
   XLXI_32 : VCC
      port map (P=>XLXN_57);
   
   XLXI_33 : AND4
      port map (I0=>d4, I1=>d3, I2=>d2, I3=>d1, O=>XLXN_22);
   
   XLXI_34 : NOR2
      port map (I0=>XLXN_48, I1=>XLXN_35, O=>sound);
   
   XLXI_35 : f01ms
      port map (CLK=>clk, CP=>XLXN_1);
   
   XLXI_38 : xzq3
      port map (d1(3 downto 0)=>XLXN_26(3 downto 0), d2(3 downto 0)=>XLXN_25(3
            downto 0), d3(3 downto 0)=>XLXN_24(3 downto 0), sel(2 downto
            0)=>wx_Dummy(2 downto 0), q(3 downto 0)=>XLXN_74(3 downto 0), wx(7
            downto 0)=>wx_DUMMY(7 downto 0));
   
   XLXI_39 : ymq
      port map (A(3 downto 0)=>XLXN_74(3 downto 0), Q(7 downto 0)=>q(7 downto
            0));
   
end BEHAVIORAL;