svpwm_top_tb.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY svpwm_top_tb IS
END svpwm_top_tb;

ARCHITECTURE behavior OF svpwm_top_tb IS 

	COMPONENT svpwm_top
	PORT(
		--
		-- input port
		--
		clk    : in std_logic;
    	reset  : in std_logic;
    	en	   : in std_logic;
    	asymstate : in std_logic;
		--		
		-- output port
		--
		vec_out : out std_logic_vector(2 downto 0);
		u_top   : out std_logic;
    	u_bot   : out std_logic;
    	v_top   : out std_logic;
    	v_bot   : out std_logic;
    	w_top   : out std_logic;
    	w_bot   : out std_logic	
		);
	END COMPONENT;

		--
		-- input port signal
		--
		signal clk    : std_logic :='0';
    	signal reset  : std_logic :='0';
    	signal en	  : std_logic :='1';
    	signal asymstate :  std_logic :='1';    	
		--		
		-- output port signal
		--
		signal vec_out : std_logic_vector(2 downto 0);
		signal u_top   : std_logic;
    	signal u_bot   : std_logic;
    	signal v_top   : std_logic;
    	signal v_bot   : std_logic;
    	signal w_top   : std_logic;
    	signal w_bot   : std_logic;
BEGIN

	uut: svpwm_top PORT MAP(
		--
		-- input port
		--
		clk    => clk,
		reset  => reset,
		en	   => en,
		asymstate => asymstate,
		--		
		-- output port
		--
		vec_out => vec_out,
		u_top => u_top,
		u_bot => u_bot,
		v_top => v_top,
		v_bot => v_bot,
		w_top => w_top,
		w_bot => w_bot
		
		);
		reset	<= '1' after 40 ns;
	clk	<= not clk after 10 ns;

	tb : PROCESS
	BEGIN
		-- Wait 100 ns for global reset to finish
			
			
		wait ;             			                 
		-- alfa <= "100000000000101000";
		-- beta <= "100000000000001000";
		-- Place stimulus here
		--wait; -- will wait forever
	END PROCESS;
END;