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Logic Analyzer 的代码
rom.vhd
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity rom is
port(address:in std_logic_vector(15 downto 0);
ltc2624 .txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primi
ir.vhd
-- ir.vhd
-- This module implements the Instruction Register (IR). IR is loaded from
-- memory on the rising edge of "clk" when "IRwrite" is asserted high. It is
-- cleared to zero when "reset" i
pci_io_virtex.vhd
--*****************************************************************************
-- FILE : PCI_IO_Virtex
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : Physical I/O Interfa
hwtb_ddr1_top.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
---
tennis.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TENNIS is
port(bain,bbin,clr,clk,souclk:in std_logic;
ballout:out std_logic_vector(7 downto 0);
countah,countal,countbh,countbl:out std_logic_v
cnt8.vhd
LIBRARY IEEE; -- 8进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT8 IS
PORT ( CLK : IN STD_LOGIC;
CQ : OU
cnt5.vhd
LIBRARY IEEE; -- 4进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT5 IS
PORT ( CLK : IN STD_LOGIC;
AA : OU
dec1.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Dec1 IS
PORT ( CLK : IN STD_LOGIC;
D : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END ;
ARCH
cnt2.vhd
LIBRARY IEEE; -- 4进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT2 IS
PORT ( CLK : IN STD_LOGIC;
CQ : OU