cnt5.vhd

来自「基于ALTERA的cyclone 系列的控制电机的实验例程」· VHDL 代码 · 共 18 行

LIBRARY IEEE;                                            -- 4进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT5 IS
    PORT ( CLK : IN STD_LOGIC;
             AA : OUT STD_LOGIC_VECTOR(4 DOWNTO 1));
END CNT5;
ARCHITECTURE behav OF CNT5 IS
    SIGNAL CQI : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
    PROCESS(CLK)
    BEGIN
       IF CLK'EVENT AND CLK = '1'  then  CQI <= CQI + 1; END IF;
    END PROCESS;
  AA <= CQI(4 DOWNTO 1);
END behav;