rom.vhd

来自「自己刚写的一个RISC的cpu」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;


entity rom is
       port(address:in std_logic_vector(15 downto 0);
            memout:out std_logic_vector(15 downto 0);
            re:in std_logic
            );
end entity rom;

architecture one of rom is
       type array2 is array (0 to 255) of std_logic_vector(15 downto 0);
       signal regf:array2:=(
                            X"1900",
                            X"4401",
                            X"4801",
                            x"6e03",
                            X"2600",
                            X"3600",
                            x"1600",
                            x"1E00",
                            x"6e01",
                            X"5000",
                            others=>X"0000"
                            );  
       begin
      process(re)
      begin     
          if(re='1') then
            memout<=regf(to_integer(unsigned(address)));
          --else  
            --memout<=(others=>'0');
         --end if;
         end if;   
       end process;                                   
end one;