pcalu.vhd

来自「自己刚写的一个RISC的cpu」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;

entity pcalu is
       port(pcalu_c    :in std_logic_vector(2 downto 0);
            pc_imm     :in std_logic_vector(15 downto 0);
            jmp_imm    :in std_logic_vector(11 downto 0); 
            comp_imm   :in std_logic_vector(7 downto 0);  
            rdm_imm    :in std_logic_vector(9 downto 0);  
            comp_out   :in std_logic;
            pcalu_out  :out std_logic_vector(15 downto 0)
             );
end pcalu;

architecture one of pcalu is
    signal pcalu_temp:std_logic_vector(3 downto 0);

   begin
      pcalu_temp<=(pcalu_c&comp_out);
   process(pcalu_temp) 
      begin
         case pcalu_temp is         
           when "0001" =>                               
              pcalu_out<=pc_imm+("00000000"& comp_imm);           
           when "0010"=>                                
              pcalu_out<=("000000"& rdm_imm);         
           when "0100"=>                                
              pcalu_out<=("0000"& jmp_imm);
           when "1000"=>                                
              pcalu_out<=pc_imm+1;
           when others=>
              pcalu_out<=pc_imm;
         end case;
    end process;
 end one;