ir.vhd

设计一个非常简单的16位CPU

-- ir.vhd

-- This module implements the Instruction Register (IR). IR is loaded from
-- memory on the rising edge of "clk" when "IRwrite" is asserted high. It is
-- cleared to zero when "reset" is asserted low. The output of PC is decoded
-- instruction.

-- Inputs: 
--    MemData   - 16-bit data to be input into IR when "IRwrite" is asserted
--    IRwrite   - 1-bit control signal
--    reset     - 1-bit reset signal which clears IR to zero when it is asserted low
--    clk       - 1-bit clock signal

-- Outputs: 
--    ins15_12  - 4-bit instruction output
--    ins11_9   - 3-bit instruction output
--    ins8_6    - 3-bit instruction output
--    ins5_3    - 3-bit instruction output
--    ins2_0    - 3-bit instruction output
--    ins5_0    - 6-bit instruction output
--    ins8_0    - 9-bit instruction output

-- Author:    Easyright
-- E-mail:    [e-mail]
-- Date:      17-08-2003
-- Copyright: http://www.EasyRight.net

------------------------------------------------------------------------------------------------------ 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ir is
  port (
    MemData:  in std_logic_vector(15 downto 0);
    IRwrite:  in std_logic;
    reset:    in std_logic;
    clk:      in std_logic;
    ins15_12: out std_logic_vector(3 downto 0);
    ins11_9, ins8_6, ins5_3, ins2_0: out std_logic_vector(2 downto 0);
    ins5_0:   out std_logic_vector(5 downto 0);
    ins8_0:   out std_logic_vector(8 downto 0)
  );
end ir;

architecture arc_ir of ir is
  signal t: std_logic_vector(15 downto 0);
begin
  process(clk, reset)
  begin
    if (reset = '0') then
      t <= "0000000000000000";
    elsif rising_edge(clk) then 
      if (IRwrite = '1') then 
        t <= MemData; 
      else
        t <= t;
      end if;
    end if;
  end process;

  process(t)
  begin
    ins15_12 <= t(15 downto 12);
    ins11_9  <= t(11 downto 9);
    ins8_6   <= t(8 downto 6);
    ins5_3   <= t(5 downto 3);
    ins2_0   <= t(2 downto 0);
    ins5_0   <= t(5 downto 0);
    ins8_0   <= t(8 downto 0);
  end process;
end arc_ir;