dec1.vhd

基于ALTERA的cyclone 系列的控制电机的实验例程

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  ENTITY Dec1 IS
    PORT ( CLK : IN STD_LOGIC;
            D  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)  ) ;
 END ;
 ARCHITECTURE one OF Dec1 IS
 SIGNAL CQ : STD_LOGIC_VECTOR(1 DOWNTO 0);
 BEGIN
   PROCESS( CQ )
    BEGIN
        CASE  CQ  IS
          WHEN "00" =>  D <= "0100" ; 
          WHEN "01" =>  D <= "0111" ; 
          WHEN "10" =>  D <= "1011" ; 
          WHEN "11" =>  D <= "1111" ; 
          WHEN OTHERS =>  NULL ;
        END CASE ;
    END PROCESS ;
 PROCESS(CLK)
    BEGIN
       IF CLK'EVENT AND CLK = '1'  then CQ <= CQ + 1; END IF;
    END PROCESS;
 END ;