ltc2624 .txt

来自「利用LTC2624 將數位信號轉類比信號」· 文本 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LTC2624 is
port(
    clk  : in std_logic; 
    rotor : in std_logic_vector(3 downto 0) ;
    DAC_CS : out std_logic;
    SPI_MOSI : out std_logic;-------SDI
    DAC_CLR : out std_logic;
    SPI_CLK : out std_logic;
	 address : out std_logic_vector(7 downto 0);
	 number : out std_logic_vector(6 downto 0);
	 dp : out std_logic
	 ) ; 
end LTC2624;

architecture Behavioral of LTC2624 is

signal i :integer range 0 to 35 :=0 ;
signal reg : std_logic_vector(24 downto 0) ;    
signal indata: std_logic_vector(3 downto 0);
signal D :std_logic_vector(2 downto 0);
signal Q :std_logic_vector(31 downto 0);
signal N :std_logic_vector(3 downto 0);
signal P :std_logic_vector(6 downto 0);
begin
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