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找到约 10,000 项符合
Logic Analyzer 的代码
ls138.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY LS138 IS
PORT(G1,G2,A,B,C:IN STD_LOGIC;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7:OUT STD_LOGIC);
tlv5636.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
---final freq 111.90HZ
ENTITY tlv5636 Is
Port(
ClkSystem : in STD_LOGIC; --输入
count_16.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT_16 IS
PORT(DISCLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNT_16;
ARCHITECTURE
count_16.tdf
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT_16 IS
PORT(DISCLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNT_16;
ARCHITECTURE
memtest.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.rand.all;
package mem is
component memTest
generic(
DATA_WIDTH : natura
ramb4_s8.vhd
-- megafunction wizard: %LPM_RAM_DQ%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAMB4_S8.vhd
v2_5.vhd
library ieee;
use ieee.std_logic_1164.all;
package Const is
constant Threshold : std_logic_vector(7 downto 0);
end Const;
v2_52.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.Const.all;
entity V2_52 is
port(Points : in std_logic_vector(7 downto 0);
IsPass : out boolean);
end V2_52;
architecture a o
lfsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use std.textio.all;
entity LFSR is
generic(BitNumber : integer := 32);
port(OutNumberA : out std_logic_vector(BitNum
v6_5.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V6_5 is
port(a : in std_logic;
b : in std_logic;
Dout : out std_logic;
Clk : in std_log