ls138.vhd

通过vhdl实现ls138硬件功能通过vhdl实现ls138硬件功能通过vhdl实现ls138硬件功能通过vhdl实现ls138硬件功能

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY LS138 IS
PORT(G1,G2,A,B,C:IN STD_LOGIC;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7:OUT STD_LOGIC);
END ENTITY LS138;
ARCHITECTURE ONE OF LS138 IS
SIGNAL ALLQ:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL abc:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
ABC<=A&B&C;
Q7<=ALLQ(0);Q6<=ALLQ(1);Q5<=ALLQ(2);Q4<=ALLQ(3);Q3<=ALLQ(4);
Q2<=ALLQ(5);Q1<=ALLQ(6);Q0<=ALLQ(7);
PROCESS(G1,G2,A,B,C)
BEGIN
IF (G1='0')AND(G2='1') THEN ALLQ<="11111111";
ELSE  CASE ABC IS
WHEN "111" => ALLQ<="11111110";
WHEN "110" => ALLQ<="11111101";
WHEN "101" => ALLQ<="11111011";

WHEN "100" => ALLQ<="11110111";
WHEN "011" => ALLQ<="11101111";
WHEN "010" => ALLQ<="11011111";
WHEN "001" => ALLQ<="10111111";
WHEN "000" => ALLQ<="01111111";
WHEN OTHERS=> NULL;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE ONE;