tlv5636.vhd

音频DA tlv5636的接口程序 经过硬件测试的成功 学习状态机对器件编程的经典

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
---final freq 111.90HZ
ENTITY tlv5636 Is
	Port(			
			ClkSystem	:		in  STD_LOGIC;  --输入系统时钟
			Reset		:		in	Std_logic;	--复位									
			
			led			:		out  std_logic_vector(7 downto 0);
			SCLK		:		out std_logic;  				
			CS			:		out std_logic;   
			
			DA_Out		:		out std_logic ;
			fs			:		out std_logic;

			transok		:		out std_logic
		);
end entity;

Architecture behav of tlv5636 is
signal addr		: std_logic_vector(11 downto 0);
signal DivideCount:integer range 0 to 71:=0;
signal ClkIn	: std_logic;
signal data 	: std_logic_vector(11 downto 0);

component rrom 
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
end component;

component da
	port
	(
			ClkSystem	:		in  STD_LOGIC;  --输入系统时钟
			Reset		:		in	Std_logic;	--复位									
			datada		:		in  std_logic_vector(11 downto 0);		
			SCLK		:		out std_logic;  				
			CS			:		out std_logic;   
			DA_Out		:		out std_logic ;
			fs			:		out std_logic;
			led			:		out  std_logic_vector(7 downto 0);
			transok		:		out std_logic
		);
end component;
begin
a:process(ClkSystem,Reset)
	begin
	  if Reset='0' then
			ClkIn<='1';
	  elsif(ClkSystem'Event and ClkSystem='1')  then		
		if(DivideCount=71)  then
			ClkIn<=not ClkIn;
			DivideCount<=0;
		else
			DivideCount<=DivideCount+1;
		end if;
	 end if;
 end process;

b:process(Reset,ClkIn)
	begin
		if Reset='0' then
			addr<=x"000";
		elsif rising_edge(ClkIn) then		
			if addr=x"fff" then
				addr<=x"000";
			else 
				addr<=addr+1;
			end if;
		end if;
	end process;
	
	rrom_u1 : rrom PORT MAP (
		address	=> addr ,
		clock	=> ClkIn,
		q		=>data 
	);
	
	da_u1	:da port map (
		ClkSystem	=>ClkSystem	,
		Reset		=>Reset	,	
		datada		=>data,		
		SCLK		=>SCLK,		
		CS			=>CS,			
		DA_Out		=>DA_Out,		
		fs			=>fs,			
		led			=>led,
		transok		=>transok	
		);	
end behav;