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Logic Analyzer 的代码
add.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add is port(
clk: in std_logic;--两个控制信号
clk1: in std_logic;
add: out std_logic_vector(7 downto 0));
end
triangle.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity triangle is port(
clk: in std_logic;
data: out std_logic_vector(7 downto 0));
end entity triangle;
arch
vhdl源代码.txt
以下为正弦波的VHDL语言编程源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sin4 is
port(clk4:in std_logic;
dd4:out integer range 255
4bit_alu.vhd
--4 bit alu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- dis_out connects to 7 seg
fbitaddr.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity fbitaddr is
Port ( a4 :
alu_2bit.vhd
--4 bit alu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- dis_out connects to 7 seg
4bit_alu.vhd
--4 bit alu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- dis_out connects to 7 seg
fbitaddr.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity fbitaddr is
Port ( a4 :
bbfifo_16x8.vhd
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
bbfifo_16x9.vhd
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 9-bit data
--
-- Version : 1.00 (derived from bbfifo_16x8 version 1.10)
-- Version Date : 10th February 2005
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchm